2 qishi123123123 qishi123123123 于 2013.06.21 09:40 提问

VHDL 16选1数据选择器

不知道哪里错了,求解释
library ieee;
use ieee.std_logic_1164.all;
entity selc is
port(DATA0,DATA1,DATA2,DATA3,DATA4,DATA5:in std_logic ;
DATA6,DATA7,DATA8,DATA9,DATA10,DATA11:in std_logic ;
DATA12,DATA13,DATA14,DATA15:in std_logic ;
sel: in std_logic(3 downto 0);
q:out std_logic);
end;
architecture bh of selc is
begin
case sel is
when"0000"=>q<=DATA0;
when"0001"=>q<=DATA1;
when"0010"=>q<=DATA2;
when"0011"=>q<=DATA3;
when"0100"=>q<=DATA4;
when"0101"=>q<=DATA5;
when"0110"=>q<=DATA6;
when"0111"=>q<=DATA7;
when"1000"=>q<=DATA8;
when"1001"=>q<=DATA9;
when"1010"=>q<=DATA10;
when"1011"=>q<=DATA11;
when"1100"=>q<=DATA12;
when"1101"=>q<=DATA13;
when"1110"=>q<=DATA14;
when others=>null;
end case;
end bh;

Csdn user default icon
上传中...
上传图片
插入图片
准确详细的回答,更有利于被提问者采纳,从而获得C币。复制、灌水、广告等回答会被删除,是时候展现真正的技术了!