这段代码是计算两个数相除，不能输出正确结果，求问错在哪里

Question

module divide_16bits(op1,op2,result
);
input [15:0] op1;
input [15:0] op2;
output reg [15:0] result;

reg error;
integer p,q,r;

reg [15:0] temp;
reg [15:0] add_result;

always @(op1 or op2)
begin
assign error = ~{|{op2}};
if(error == 1)
result[15:0] = 16'h0eb0;
else
begin
for(p = 15;p >= 0;p = p - 1)
result[p] = 1'b0;
p = 16;
q = 16;
while((p >= 0) & (op1[p] == 0))
p = p - 1;
while((q != 0) & (op2[q] == 0))
q = q - 1;
if(p >= q)
begin
add_result[15:0] = 16'h0;
for(r = p - q;r >= 0;r = r - 1)
begin
temp = add_result + (op2 << r);
if( op1 >= temp)
begin
result[r] = 1'b1;
add_result = add_result + (op2 << r);
end
end

end
end

end
endmodule

Answer 1

我发现是这段代码出问题了，代码从c语言角度能达到目标，但是verilog语言无法实现
while((p >= 0) && (op1[p] == 0))
p = p - 1;
while((q != 0) && (op2[q] == 0))
q = q - 1;