2 apprentices apprentices 于 2016.02.28 21:50 提问

这段代码中二,四,八分频和十六分频有什么意思?

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

ENTITY LED IS
PORT (clk,rst:IN std_logic;
inp: in std_logic_vector(1 downto 0);
output : OUT std_logic_vector(7 downto 0) );
END LED;

ARCHITECTURE ONE OF LED IS
SIGNAL clk_2,clk_4,clk_8,clk_16,q:STD_LOGIC;
SIGNAL OUTPUT3: std_logic_vector(6 downto 0);
SIGNAL output1 :std_logic;
SIGNAL output2 :std_logic_vector(6 downto 0) ;
SIGNAL e:integer range 0 to 33;
Begin

--2分频
p1:process(clk,rst)
variable a:integer range 0 to 20;

begin
if rst='1' then clk_2<='0';

else if clk'event and clk='1'then

if a>=1 then

a:=0;
clk_2<='1';
else a:=a+1;
clk_2<='0';
end if;
end if;
end if;
end process p1;

--4分频
p2:process(clk,rst)

    variable b:integer range 0 to 20;  
    begin 
        if rst='1' then
          clk_4<='0'; 
        else 
             if clk'event and clk='1'then   
                 if b>=3 then  
                      b:=0;
                    clk_4<='1';  
                 else  
                      b:=b+1;  
                      clk_4<='0'; 
                end if; 
            end if;  
       end if; 
  end process p2; 

--8分频
p3:process(clk,rst)

variable c:integer range 0 to 20;

begin
if rst='1' then
clk_8<='0';

else
if clk'event and clk='1'then

if c>=7 then

c:=0;

clk_8<='1';

else
c:=c+1;
clk_8<='0';

end if;
end if;
end if;
end process p3;

--16分频
p4:process(clk,rst)

variable d:integer range 0 to 20;
begin
if rst='1' then

clk_16<='0';

else if (clk'event and clk='1')then

if d>=15 then
d:=0;
clk_16<='1';

else d:=d+1;
clk_16<='0';
end if;

end if;

end if;
end process p4;

--4选1

PROCESS (rst,inp)
BEGIN
if(rst='1') then output1<='0';
else
case inp is
when "00"=>output1<=clk_2;OUTPUT3<="0111111";

           when "01"=>output1<=clk_4;OUTPUT3<="0000110"; 
           when "10"=>output1<=clk_8;OUTPUT3<="1011011"; 
           when "11"=>output1<=clk_16;OUTPUT3<="1001111";  
           when others=>null;
     end case;
  end if;
  output2<=OUTPUT3;
END PROCESS;

--33进制计数器
PROCESS (rst,q)

variable temp:integer range 0 to 33;

      BEGIN  
       q<=output1;
         IF rst='1' THEN temp:=0;   
           ELSIF (q'event and q='1') THEN         
                  temp:=temp+1;  
               if(temp=33) then temp:=0;            
               end if;  
         END IF; 
      e<=temp; 
   END PROCESS; 

    PROCESS (e)   
    BEGIN 
          if rst='1' then output<="11111110"; 
          else 
           case e is 
             when 0=>output<="11111110";    
             when 1=>output<="01111111"; 
             when 2=>output<="10111111";  
             when 3=>output<="11011111"; 
             when 4=>output<="11101111";
             when 5=>output<="11110111";   
             when 6=>output<="11111011";   
             when 7=>output<="11111101";
             when 8=>output<="11111110"; 
             when 9=>output<="11111111";  
             when 10=>output<="01111111";   
             when 11=>output<="00111111";  
             when 12=>output<="00011111";  
             when 13=>output<="00001111";   
             when 14=>output<="00000111";   
             when 15=>output<="00000011";   
             when 16=>output<="00000001";
             when 17=>output<="00000000";
             when 18=>output<="10000000"; 
             when 19=>output<="11000000";  
             when 20=>output<="11100000";   
             when 21=>output<="11110000"; 
             when 22=>output<="11111000";   
             when 23=>output<="11111100"; 
             when 24=>output<="11111110";
             when 25=>output<="10000000";
             when 26=>output<="01000000"; 
             when 27=>output<="00100000";   
             when 28=>output<="00010000";
             when 29=>output<="00001000";   
             when 30=>output<="00000100";   
             when 31=>output<="00000010";
             when 32=>output<="00000001";   
             when others=>null; 
          end case; 
        end if;
   end process; 

end ONE;

2个回答

caozhy
caozhy   Ds   Rxr 2016.02.28 22:52

就是给一个时钟信号,产生一个时钟信号,产生的时钟速度是原来的1/4 1/8 1/16...
原理是增加一个计数器,比如8分频,如果计数器计数在0-7,就输出0,8-15输出1,结果就是产生了一个1/8的0-1时钟信号。

apprentices
apprentices   2016.03.03 14:40

那么如何设定时间呢?

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