2 zhangyu nefu zhangyu_nefu 于 2013.12.19 18:24 提问

S3C2440CPU 仿GT2440开发板u-boot启动程序,串口无信息输出

CPU:S3C2440
SDRAM:2个MT48LC32M16A2TG-75IT
NANDFLASH:1个K9F2G08U0B

电路连接图同GT2440一样,就是换了个大点的SDRAM,硬件电路(包括串口)无任何问题,问题出现在软件,由于软件代码是从GT2440的u-boot移植过来的,可以再GT2440上正常运行,用示波器量SDRAM时钟管脚在刚上电时波形的时间明显比正常运行的GT2440板子上SDRAM的CLK管脚时间短,怀疑是SDRAM初始化配置的缘故,但自身感觉无任何问题,由于从GT2440上移植,所以宏定义只需要更改涉及SDRAM大小的地方而已。很奇怪,没有思路了,
lowlevel.S代码如下:
#include
#include

/* some parameters for the board */

/*
*

  • Taken from linux/arch/arm/boot/compressed/head-s3c2410.S *
  • Copyright (C) 2002 Samsung Electronics SW.LEE hitchcar@sec.samsung.com * */

#define BWSCON 0x48000000

/* BWSCON */
#define DW8 (0x0)
#define DW16 (0x1)
#define DW32 (0x2)
#define WAIT (0x1<<2)
#define UBLB (0x1<<3)

#define B1_BWSCON (DW32)
#define B2_BWSCON (DW16)
#define B3_BWSCON (DW32 + WAIT)
#define B4_BWSCON (DW16)
#define B5_BWSCON (DW16)
#define B6_BWSCON (DW32)
#define B7_BWSCON (DW32)

/* BANK0CON /
#define B0_Tacs 0x0 /
0clk /
#define B0_Tcos 0x0 /
0clk /
#define B0_Tacc 0x7 /
14clk /
#define B0_Tcoh 0x0 /
0clk /
#define B0_Tah 0x0 /
0clk /
#define B0_Tacp 0x0
#define B0_PMC 0x0 /
normal */

/* BANK1CON /
#define B1_Tacs 0x0 /
0clk /
#define B1_Tcos 0x0 /
0clk /
#define B1_Tacc 0x7 /
14clk /
#define B1_Tcoh 0x0 /
0clk /
#define B1_Tah 0x0 /
0clk */
#define B1_Tacp 0x0
#define B1_PMC 0x0

#define B2_Tacs 0x0
#define B2_Tcos 0x0
#define B2_Tacc 0x7
#define B2_Tcoh 0x0
#define B2_Tah 0x0
#define B2_Tacp 0x0
#define B2_PMC 0x0

#define B3_Tacs 0x0 /* 0clk /
#define B3_Tcos 0x3 /
4clk /
#define B3_Tacc 0x7 /
14clk /
#define B3_Tcoh 0x1 /
1clk /
#define B3_Tah 0x0 /
0clk /
#define B3_Tacp 0x3 /
6clk /
#define B3_PMC 0x0 /
normal */

#define B4_Tacs 0x0 /* 0clk /
#define B4_Tcos 0x0 /
0clk /
#define B4_Tacc 0x7 /
14clk /
#define B4_Tcoh 0x0 /
0clk /
#define B4_Tah 0x0 /
0clk /
#define B4_Tacp 0x0
#define B4_PMC 0x0 /
normal */

#define B5_Tacs 0x0 /* 0clk /
#define B5_Tcos 0x0 /
0clk /
#define B5_Tacc 0x7 /
14clk /
#define B5_Tcoh 0x0 /
0clk /
#define B5_Tah 0x0 /
0clk /
#define B5_Tacp 0x0
#define B5_PMC 0x0 /
normal */

#define B6_MT 0x3 /* SDRAM /
#define B6_Trcd 0x1
#define B6_SCAN 0x2 /
2bit */

#define B7_MT 0x3 /* SDRAM /
#define B7_Trcd 0x1 /
3clk /
#define B7_SCAN 0x2 /
10bit */

/* REFRESH parameter /
#define REFEN 0x1 /
Refresh enable /
#define TREFMD 0x0 /
CBR(CAS before RAS)/Auto refresh /
#define Trp 0x0 /
2clk /
#define Trc 0x3 /
7clk /
#define Tchr 0x2 /
3clk /
/
#define REFCNT 1113 // period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) /
#define REFCNT 1113 /
period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */

_TEXT_BASE:
.word TEXT_BASE

.globl lowlevel_init
lowlevel_init:
/* memory control configuration /
/
make r0 relative the current location so that it /
/
reads SMRDATA out of FLASH rather than memory ! /
ldr r0, =SMRDATA
ldr r1, _TEXT_BASE
sub r0, r0, r1
ldr r1, =BWSCON /
Bus Width Status Controller */
add r2, r0, #13*4
0:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne 0b

/* everything is fine now */
mov pc, lr

.ltorg

/* the literal pools origin */

SMRDATA:
.word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
.word 0x32
.word 0x30
.word 0x30

1个回答

XIAO_PING_PING
XIAO_PING_PING   2014.05.27 22:14

不知道你问题解决了没有,你这样子是看不出什么端倪的,我介意你用AXD加Jlink调试,参考如下:
http://blog.csdn.net/xiao_ping_ping/article/details/27118307

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