LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY xyw10218104 IS
PORT(clk_1:IN STD_LOGIC;
d0,d1,d2,d3,d4,d5,d6,d7:buffer STD_LOGIC_VECTOR(3 DOWNTO 0));
END xyw10218104;
ARCHITECTURE one OF xyw10218104 IS
begin
process(clk_1)
begin
d7<="1000";
d6<="0111";
d5<="0110";
d4<="0101";
d3<="0100";
d2<="0011";
d1<="0010";
d0<="0001";
if(clk_1'event and clk_1='1') then
d7<=d0;
d6<=d1;
d5<=d2;
d4<=d3;
d3<=d4;
d2<=d5;
d1<=d6;
d0<=d7;
END IF;
END PROCESS;
END one;
出现这样的错误不明白是什么原因 应该怎么修改才能正确赋初值呢?