verilog简单错误修改，求大神，急急急

Question

我自己写的一个小程序，怎么改都改不对，求助大神
module shouhuo (k1,k2,a,b,clk,out,out_1,out_2,rst_n);
input k1,k2,out,clk,rst_n;
input [3:0]a,b;
output out_1; //输出饮料
output out_2; //找零

reg out_1,out_2;
always@(posedge k1 or posedge out)
begin
if(out==1)
a<=0; //饮料出来后计数器清零
else a<=a+4'b1;
end
always@(posedge k2 or posedge out)
begin
if(out==1)
b<=0; //饮料出来后计数值清零
else b<=b+4'b1;
end
always@(posedge clk or negedge rst_n)

begin
if(!rst_n)
a<=0;
b<=0;
else if(a==3)
begin
out_1<=1;
out<=out_1; //按下3次K1，输出饮料
end
else if(a==1&&b==1)
begin
out_1<=1;
out<=out_1; //按下一次k1，一次k2，输出饮料
end
else if(a==2&&b==1)
begin
out_1<=1;
out_2<=1;
out<=out_1;
end //按下两次k1，一次k2，输出饮料，找零
else if(a==0&&b==2)
begin
out_1<=1;
out_2<=1;
out<=out_1;
end //按下两次k2，输出饮料，找零
end

endmodule
错误提示是：
Error (10170): Verilog HDL syntax error at shouhuo.v(25) near text "else"; expecting "end"

Error (10112): Ignored design unit "shouhuo" at shouhuo.v(1) due to previous errors

Answer 1

不是，都配套了 ， 我把头文件
module shouhuo (k1,k2,a,b,clk,out,out_1,out_2,rst_n);改成 module shouhuo之后之前的错误全没了，变成了
Error (10170): Verilog HDL syntax error at shouhuo.v(2) near text "input"; expecting ";"
第二行语法错误，这是我自学的 看不出哪里的语法有错误