2 u014767251 u014767251 于 2014.04.25 14:45 提问

CIC设计代码不懂 求助啊

这是从该社区下载下来的CIC代码 但是有点看不懂 所以哪位大神帮帮忙 给注释一下吧
library IEEE;
use IEEE.std_LOGIC_1164.ALL;
use IEEE.std_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CIC is
Port(sysclk:in std_logic;
ena:in std_logic;
datain:in std_logic_vector(11 downto 0);
dataine:out std_logic_vector(15 downto 0);
dataout:out std_logic_vector(15 downto 0));
end CIC;

architecture Behavioral of CIC is
signal datainext: std_logic_vector(27 downto 0);--29
signal acca: std_logic_vector(27 downto 0); --29
signal accb: std_logic_vector(27 downto 0); ---24
--signal accb_delay:std__logic_vector(27 downto 0);
signal accc: std_logic_vector(27 downto 0);
--signal accc_delay:std logic_vector(27 downto 0);
signal accd: std_logic_vector(27 downto 0);
signal accd_delay: std_logic_vector(27 downto 0);
signal combl: std_logic_vector(27 downto 0);
---signal comble: std logic vector(17 downto 0);
signal combl_delay: std_logic_vector(27 downto 0);---13
signal comb2: std_logic_vector(27 downto 0);
signal comb2_delay: std_logic_vector(27 downto 0);---12
signal comb3: std_logic_vector(27 downto 0);---12
Signal comb3_delay: std_logic_vector(27 downto 0);
Signal comb4: std_logic_vector(27 downto 0);
Signal comb4_delay: std_logic_vector(27 downto 0);
Signal decimate_count:std_logic_vector(3 downto 0);

begin

datainext(27)<=datain(11);
datainext(26)<=datain(11);
datainext(25)<=datain(11);
datainext(24)<=datain(11);
datainext(23)<=datain(11);
datainext(22)<=datain(11);
datainext(21)<=datain(11);
datainext(20)<=datain(11);
datainext(19)<=datain(11);
datainext(18)<=datain(11);
datainext(17)<=datain(11);
datainext(16)<=datain(11);
datainext(15)<=datain(11);
datainext(14)<=datain(11);
datainext(13)<=datain(11);
datainext(12)<=datain(11);
datainext(11 downto 0)<=datain(11 downto 0);

dataout<=comb4(27 downto 12);--(29 downto 14);

---dataine<=datain; --datain&"0000"
process(sysclk)
begin
IF ena='1' then
if sysclk='1' and sysclk'event then
decimate_count<=decimate_count+1;
---if sampleclk2=’1’then
acca<=acca+datainext;
---acca—delay<2accaj
accb<=accb+acca;
accc<=accc+accb;
accd<=accd+accc;
if decimate_count="1111"then ----Decimation Ratio=16
accd_delay<=accd;
combl_delay<=combl;
comb2_delay<=comb2;
comb3_delay<=comb3;
combl<=accd-accd_delay;
comb2<=combl-combl_delay;
comb3<=comb2-comb2_delay;
comb4<=comb3-comb3_delay;

end if;

end if;
end if;
end process;
end Behavioral;

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