** Fatal: Internal Error - vopt returned success but vsim could not find a design to simulate!. Please contact customer support for further assistance.
Error loading design
Error: Error loading design
Pausing macro execution
MACRO ./aaa_run_msim_rtl_verilog.do PAUSED at line 40
新手刚开始学这个,前面都是按照例题流程做的,最后仿真不了了,这是什么错误啊。求大佬教教···
下面是testbench修改的部分
initial
begin
#0 CLK_50M=1'b0;
#10000 RST_N=1'b0;
#10000 RST_N=1'b1;
#10000000 $stop;
end
always#10000
begin
CLK_50M=~CLK_50M;
end
endmodule
程序是
module aaa
(
//输入端口
CLK_50M,RST_N,
//输出端口
LED1
);
//外部端口声明
input CLK_50M;
input RST_N;
output LED1;
//内部端口声明
reg[26:0] time_cnt;//控制LED闪烁频率的定时计数器
reg[26:0] time_cnt_n;//time_cnt的下一个状态
reg led_reg; //用来控制LED亮灭的显示寄存器
reg led_reg_n; //led_reg下一个状态
//设定定时器的时间为1s,计算方法为(1*10^6)us/(1/50)us 50MHz的晶振
parameter SET_TIME_1S=27'd50;
//逻辑功能实现
//时序电路,用来给time_cnt寄存器赋值
always @ (posedge CLK_50M or negedge RST_N)
begin
if(!RST_N) //判断复位
time_cnt <= 27'h0;//初始化值
else
time_cnt <= time_cnt_n;//赋值
end
//组合电路,实现1s定时计数器
always@(*)
begin
if(time_cnt==SET_TIME_1S)
time_cnt_n=27'h0;
else
time_cnt_n=time_cnt+27'h1;
end
//时序电路,用来给led_reg寄存器赋值
always@(posedge CLK_50M or negedge RST_N)
begin
if(!RST_N)
led_reg<=1'b0;
else
led_reg<=led_reg_n;
end
//组合底哪路,判断时间,控制LED亮灭
always@(*)
begin
if(time_cnt==SET_TIME_1S)//判断1s时间
led_reg_n=~led_reg;
else
led_reg_n=led_reg;//如果到达1s,寄存器将会改变LED的原状态,如果未到1s,显示寄存器保持LED原状态
end
assign LED1=led_reg;//最后,将显示寄存器的赋值给端口LED1
endmodule