课设任务,中间有一部分是用三个开关n0n1n2给中间值temp赋值为00,01,10
/*
clk:时钟信号
n0,n1,n2:密码输入信号
lock:状态显示信号
reset:复位信号
set:密码确认信号
*/
module code(lock,warning,num1,num2,num3,num4,clkin,n0,n1,n2,set,reset,close,temp);
input n0,n1,n2,set,reset,clkin,close;
output reg [1:0]temp;
output reg [1:0]num1,num2,num3,num4;
output reg lock,warning;
reg [1:0]i;
always@(posedge n0||n1||n2)
begin
case({n2,n1,n0})
3'b001:temp<=2'b00;
3'b010:temp<=2'b01;
3'b100:temp<=2'b10;
endcase
end
begin
case(i)
2'b00:begin
num1<=temp;
i<=1;
end
2'b01:begin
num2<=temp;
i<=2;
end
2'b10:begin
num3<=temp;
i<=3;
end
2'b11:begin
num4<=temp;
i<=0;
end
default: i<=2'b00;
endcase
end
always@(*)
begin
if(!lock&&set)
begin
if({(num4==2'b01)&&(num3==2'b00)&&(num2==2'b01)&&(num1==2'b01)})
lock<=1;
else
begin
lock<=0;
warning<=1;
end
end
if(lock&&close)
lock<=0;
if(reset)
warning<=0;
num1<=0;
num2<=0;
num3<=0;
num4<=0;
i<=2'b00;
end
endmodule
synplify时,automake log里出现这样的提示:
@W: CG1160 :"C:\users\a2763\documents\tencent files\2763739926\filerecv\light\code.v":14:16:14:26|Found complex event expression
@W: CL118 :"C:\users\a2763\documents\tencent files\2763739926\filerecv\light\code.v":58:3:58:4|Latch generated from always block for signal warning; possible missing assignment in an if or case statement.
@W: CL207 :"C:\users\a2763\documents\tencent files\2763739926\filerecv\light\code.v":56:3:56:4|All reachable assignments to lock assign 0, register removed by optimization.
@W: CL159 :"C:\users\a2763\documents\tencent files\2763739926\filerecv\light\code.v":9:25:9:29|Input clkin is unused
@W: CL159 :"C:\users\a2763\documents\tencent files\2763739926\filerecv\light\code.v":9:31:9:35|Input close is unused
@W: MT462 :|Net set_c appears to be an unidentified clock source. Assuming default frequency.
跑波形,发现temp总是为0
如果在case({n2,n1,n0})之前加个temp<=2'b11;波形就会变成这样
这个bug卡了好几天了,课设死线将至,万策尽yi