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2019-12-16 18:52 浏览 265

Verilog 状态机代码编译不过问题在哪?

Verilog编写状态机的程序如下,始终有错误,求解决

module fsm(clk, button0, button1, UNLOCK);
input button0,button1;
output UNLOCK;

//define state space
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;

//define clk
reg clk = 0;
always #50 clk = ~clk;

//internal variable
reg [1:0] current_state;
reg [1:0] next_state;
wire button0;
wire button1;
reg IN0 = button0;
reg IN1 = button1;
reg current_OUT0;
reg current_OUT1;
reg next_OUT0;
reg next_OUT1;

//transition
always @(posedge clk)
begin
IN0 = button0;
IN1 = button1;
end

always @(posedge IN0)
begin
current_OUT0 = next_OUT0;
next_OUT0 <= 1'b1;
#50 next_OUT0 <= 1'b0;
zero = current_OUT0;
end

always @(posedge IN1)
begin
current_OUT1 = next_OUT1;
next_OUT1 <= 1'b1;
#50 next_OUT1 <= 1'b0;
one = current_OUT1;
end

next_state = current_state;

//next state decision
always @(current_state)
begin
case(current_state)
S0:
begin
if(button0) next_state <= S3;
else next_state <= S0;
end

S1:
begin
    if(button1)  next_state = S0;
    else if(button0)  next_state = S2;
    else  next_state = S1;
end

S2:
begin
    if(button1)  next_state = S1;
    else if(button0)  next_state = S3;
    else  next_state = S2;
end

S3:
begin
    if(button1)  next_state = S0;
    else  next_state = S3;
end

endcase

end

//action
wire UNLOCK;
assign UNLOCK = (current_state == S2) ? 1'b1 : 1'b0;

endmodule

提示的错误是
Error (10170): Verilog HDL syntax error at try1.v(50) near text "="; expecting ".", or "("
Error (10112): Ignored design unit "fsm" at try1.v(1) due to previous errors

请问有人帮忙看一下吗

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1条回答 默认 最新

  • caozhy 从今以后生命中的每一秒都属于我爱的人 2019-12-17 00:52

    找到try1.v(50),也就是try1.v的第50行,检查下=附近,有语法错误

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