VHDL,ISE设计16位运算器,求代码注释?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port ( A : in STD_LOGIC_VECTOR(15 downto 0);
B : in STD_LOGIC_VECTOR(15 downto 0);
Y : inout STD_LOGIC_VECTOR(15 downto 0);
FINISHED : inout STD_LOGIC :='0';
ENABLED : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR(3 downto 0);
OFS : out STD_LOGIC;
CFS : out STD_LOGIC;
ZFS : out STD_LOGIC;
SFS : out STD_LOGIC);
end ALU;
architecture Behavioral of ALU is
begin
PROCESS(ENABLED)
VARIABLE temp : STD_LOGIC;
VARIABLE vec_15 : STD_LOGIC_VECTOR(14 DOWNTO 0);
VARIABLE int_A, int_B, int_Y : INTEGER RANGE 0 TO 65535;
BEGIN
IF(ENABLED = '1') THEN
FINISHED <= '0';
OFS <= '0';
CFS <= '0';
ZFS <= '0';
SFS <= '0';
int_A := CONV_INTEGER(A);
int_B := CONV_INTEGER(B);
CASE OP IS
WHEN "0000" => --ADD
Y <= A+B;
--int_Y := int_A + int_B;
--Y <= CONV_STD_LOGIC_VECTOR(int_Y,16);
if(A(15)='0' and B(15)='0' and Y(15)='1') then OFS <= '1'; end if;
if(A(15)='1' and B(15)='1' and Y(15)='0') then OFS <= '1'; CFS<='1'; end if;
if(Y = "0000000000000000") then ZFS <= '1'; end if;
if(Y(15) = '1') then SFS <= '1'; end if;
FINISHED <= '1';
WHEN "0001" => --SUB
int_Y := int_A - int_B;
if(int_Y = 0) then ZFS <= '1'; end if;
if(int_Y < 0) then SFS <= '1'; end if;
Y <= CONV_STD_LOGIC_VECTOR(int_Y,16);
FINISHED <= '1';
WHEN "0010" => --AND
Y <= (A AND B);
if(CONV_INTEGER(Y) = 0) then ZFS <= '1'; end if;
if(CONV_INTEGER(Y) < 0) then SFS <= '1'; end if;
FINISHED <= '1';
WHEN "0011" => --OR
Y <= A OR B;
FINISHED <= '1';
WHEN "0100" => --XOR
Y <= A XOR B;
FINISHED <= '1';
WHEN "0101" => --NOT
Y <= NOT A;
FINISHED <= '1';
WHEN "0110" => --SLL
if(B(3 downto 0) = "0000") then
Y <= TO_STDLOGICVECTOR(To_bitvector(A) SLL CONV_INTEGER(B(3 downto 0)));
else
Y <= TO_STDLOGICVECTOR(To_bitvector(A) SLL 1);
end if;
FINISHED <= '1';
WHEN "0111" => --SLA
if(B(3 downto 0) = "0000") then
Y <= TO_STDLOGICVECTOR(To_bitvector(A) SLA CONV_INTEGER(B(3 downto 0)));
else
Y <= TO_STDLOGICVECTOR(To_bitvector(A) SLA 1);
end if;
FINISHED <= '1';
WHEN "1000" => --SRL
if(B(3 downto 0) = "0000") then
Y <= TO_STDLOGICVECTOR(To_bitvector(A) SRL CONV_INTEGER(B(3 downto 0)));
else
Y <= TO_STDLOGICVECTOR(To_bitvector(A) SRL 1);
end if;
FINISHED <= '1';
WHEN "1001" => --SRA
if(B(3 downto 0) = "0000") then
Y <= TO_STDLOGICVECTOR(To_bitvector(A) SRA CONV_INTEGER(B(3 downto 0)));
else
Y <= TO_STDLOGICVECTOR(To_bitvector(A) SRA 1);
end if;
FINISHED <= '1';
WHEN "1010" => --ROL
if(B(3 downto 0) = "0000") then
Y <= TO_STDLOGICVECTOR(To_bitvector(A) ROL CONV_INTEGER(B(3 downto 0)));
else
Y <= TO_STDLOGICVECTOR(To_bitvector(A) ROL 1);
end if;
FINISHED <= '1';
WHEN OTHERS =>
Y <= "0000000000000000";
FINISHED <= '1';
END CASE;
END IF;
END PROCESS;
end Behavioral;

查看全部
qq_43643991
qq_43643991
2020/06/19 12:22
  • 开发语言
  • 点赞
  • 收藏
  • 回答
    私信
满意答案
查看全部

1个回复