jiaotang1992
2015-05-13 02:33
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基于vhdl的交通灯控制程序,需要管教配置图,

基于vhdl的交通灯控制程序,需要管教配置图,,能在实验箱上实现

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  • blownewbee 2015-05-13 02:37
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  • jiaotang1992 2015-05-16 02:22

    1.时钟脉冲发生电路
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    entity shizhong is
    port(reset:in std_logic;
    clk:in std_logic;
    ena_scan:out std_logic;
    ena_1hz:out std_logic;
    flash_1hz:out std_logic);
    end;
    architecture bhv of shizhong is
    constant scan_bit:positive:=2;
    constant scan_val:positive:=4;
    constant two_hz_bit:positive:=7;
    constant two_hz_val:positive:=125;
    signal clk_scan_ff:std_logic_vector(scan_bit-1 downto 0);
    signal clk_2hz_ff:std_logic_vector(two_hz_bit-1 downto 0);
    signal ena_s:std_logic;
    signal ena_one:std_logic;
    signal ena_two:std_logic;
    begin
    process(reset,clk)
    begin
    if reset='1' then
    clk_scan_ff<="00";
    ena_s<='0';
    elsif (clk'event and clk='1') then
    if clk_scan_ff>=scan_val-1 then
    clk_scan_ff<="00";
    ena_s<='1';
    else
    clk_scan_ff<=clk_scan_ff+1;
    ena_s<='0';
    end if;
    end if;
    end process;
    ena_scan<=ena_s;
    process(reset,clk,ena_s)
    begin
    if reset='1' then
    ena_one<='0';
    ena_two<='0';
    clk_2hz_ff<="0000000";
    elsif (clk'event and clk='1') then
    if ena_s='1' then
    if clk_2hz_ff>=two_hz_val-1 then
    clk_2hz_ff<="0000000";
    ena_two<='1';
    ena_one<=not ena_one;
    else
    clk_2hz_ff<=clk_2hz_ff+1;
    ena_two<='0';
    ena_one<=ena_one;
    end if;
    end if;
    end if;
    end process;
    ena_1hz<=ena_one and ena_two and ena_s;
    flash_1hz<=ena_one;
    end;

    2.计数秒数选择电路
    library ieee;
    use ieee.std_logic_1164.all
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;
    entity jishu is
    port(reset:in std_logic;
    clk:in std_logic;
    ena_scan:in std_logic;
    recount:in std_logic;
    sign_state:in std_logic_vector(2 downto 0);
    load:out std_logic_vector(7 downto 0));
    end;
    architecture bhv of jishu is
    constant redew_time:integer:=15;
    constant yellowew_time:integer:=5;
    constant greenew_time:integer:=25;
    constant redsn_time:integer:=15;
    constant yellowsn_time:integer:=5;
    constant greensn_time:integer:=25;
    begin
    process(reset,clk)
    begin
    if reset='1' then
    load<="00000000";
    elsif (clk'event and clk='1') then
    if (ena_scan='1' and recount='1') then
    case sign_state is
    when "000"=>load<=conv_std_logic_vector(greensn_time,8);
    when "001"=>load<=conv_std_logic_vector(yellowsn_time,8);
    when "010"=>load<=conv_std_logic_vector(redsn_time,8);
    when "011"=>load<=conv_std_logic_vector(redew_time,8);
    when "100"=>load<=conv_std_logic_vector(yellowew_time,8);
    when "101"=>load<=conv_std_logic_vector(greenew_time,8);
    when others=>load<=conv_std_logic_vector(yellowsn_time,8);
    end case;
    end if;
    end if;
    end process;
    end;
    3.倒计时控制电路程序
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;
    entity daojishi is
    port(reset:in std_logic;
    clk:in std_logic;
    ena_1hz:in std_logic;
    recount:in std_logic;
    load:in std_logic_vector(7 downto 0);
    led:out std_logic_vector(24 downto 0);
    next_state:out std_logic);
    end;
    architecture bhv of daojishi is
    signal cnt_ff:std_logic_vector(7 downto 0);
    begin
    process(clk,reset)
    begin
    if(reset='1') then
    cnt_ff<="00000000";
    led<="0000000000000000000000000";
    elsif(clk'event and clk='1') then
    if ena_1hz='1' then
    if(recount='1') then
    cnt_ff<=load-1;
    else cnt_ff<=cnt_ff-1;
    end if;
    end if;
    case conv_integer(cnt_ff) is
    when 0=>led(24 downto 0)<="1000000000000000000000000";
    when 1=>led(24 downto 0)<="1100000000000000000000000";
    when 2=>led(24 downto 0)<="1110000000000000000000000";
    when 3=>led(24 downto 0)<="1111000000000000000000000";
    when 4=>led(24 downto 0)<="1111100000000000000000000";
    when 5=>led(24 downto 0)<="1111110000000000000000000";
    when 6=>led(24 downto 0)<="1111111000000000000000000";
    when 7=>led(24 downto 0)<="1111111100000000000000000";
    when 8=>led(24 downto 0)<="1111111110000000000000000";
    when 9=>led(24 downto 0)<="1111111111000000000000000";
    when 10=>led(24 downto 0)<="1111111111100000000000000";
    when 11=>led(24 downto 0)<="1111111111110000000000000";
    when 12=>led(24 downto 0)<="1111111111111000000000000";
    when 13=>led(24 downto 0)<="1111111111111100000000000";
    when 14=>led(24 downto 0)<="1111111111111110000000000";
    when 15=>led(24 downto 0)<="1111111111111111000000000";
    when 16=>led(24 downto 0)<="1111111111111111100000000";
    when 17=>led(24 downto 0)<="1111111111111111110000000";
    when 18=>led(24 downto 0)<="1111111111111111111000000";
    when 19=>led(24 downto 0)<="1111111111111111111100000";
    when 20=>led(24 downto 0)<="1111111111111111111110000";
    when 21=>led(24 downto 0)<="1111111111111111111111000";
    when 22=>led(24 downto 0)<="1111111111111111111111100";
    when 23=>led(24 downto 0)<="1111111111111111111111110";
    when 24=>led(24 downto 0)<="1111111111111111111111111";
    when others=>led(24 downto 0)<="0000000000000000000000000";
    end case;
    end if;
    end process;
    next_state<='1' when cnt_ff=1 else '0';
    end;
    4.红绿灯信号控制电路
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    entity honglvdeng is
    port(reset:in std_logic;
    clk:in std_logic;
    ena_scan:in std_logic;
    ena_1hz:in std_logic;
    flash_1hz:in std_logic;
    a_m:in std_logic;
    st_butt:in std_logic;
    next_state:in std_logic;
    recount:out std_logic;
    sign_state:out std_logic_vector(2 downto 0);
    red:out std_logic_vector(1 downto 0);
    green:out std_logic_vector(1 downto 0);
    yellow:out std_logic_vector(1 downto 0));
    end;
    architecture bhv of honglvdeng is
    type sreg0_type is (rewgsn, rewysn, gewrsn, yewrsn, yewysn, yewgsn, gewysn, rewrsn);
    signal state:sreg0_type;
    signal st_transfer:std_logic;
    signal light:std_logic_vector(5 downto 0);
    begin
    process(reset,clk,ena_scan,st_butt)
    variable rebn_ff:std_logic_vector(5 downto 0);
    begin
    if (st_butt='1'or reset='1') then
    rebn_ff:="111111";
    st_transfer<='0';
    elsif (clk'event and clk='1') then
    if (ena_scan='1') then
    if (rebn_ff>=3) then
    rebn_ff:=rebn_ff-1;
    st_transfer<='0';
    elsif(rebn_ff=2) then
    rebn_ff:=rebn_ff-1;
    st_transfer<='1';
    else
    rebn_ff:=rebn_ff;
    st_transfer<='0';
    end if;
    end if;
    end if;
    end process;
    process(clk,ena_1hz,reset)
    begin
    if (reset='1') then
    state<=rewgsn;
    sign_state<="011";
    recount<='1';
    else
    if (clk'event and clk='1') then
    case state is
    when rewgsn=>
    if (a_m='1' and ena_1hz='1') then
    if (next_state='1') then
    recount<='1';
    state<=rewysn;
    sign_state<="011";
    else
    recount<='0';
    state<=rewgsn;
    end if;
    elsif (a_m='0' and ena_scan='1') then
    if (st_transfer='0') then
    recount<='1';
    state<=rewgsn;
    else
    recount<='1';
    state<=rewysn;
    sign_state<="011";
    end if;
    end if;
    when rewysn=>
    if (a_m='1' and ena_1hz='1') then
    if (next_state='1') then
    recount<='1';
    state<=gewrsn;
    sign_state<="101";
    else
    recount<='0';
    state<=rewysn;
    end if;
    elsif (a_m='0' and ena_scan='1') then
    if (st_transfer='0') then
    recount<='1';
    state<=rewysn;
    else
    recount<='1';
    state<=gewrsn;
    sign_state<="101";
    end if;
    end if;
    when gewrsn=>
    if (a_m='1' and ena_1hz='1') then
    if (next_state='1') then
    recount<='1';
    state<=yewrsn;
    sign_state<="110";
    else
    recount<='0';
    state<=gewrsn;
    end if;
    elsif (a_m='0' and ena_scan='1') then
    if (st_transfer='0') then
    state<=gewrsn;
    else
    recount<='1';
    state<=yewrsn;
    sign_state<="110";
    end if;
    end if;
    when yewrsn=>
    if (a_m='1' and ena_1hz='1') then
    if (next_state='1') then
    recount<='1';
    state<=rewgsn;
    sign_state<="001";
    else
    recount<='0';
    state<=yewrsn;
    end if;
    elsif (a_m='0' and ena_scan='1') then
    if (st_transfer='0') then
    recount<='1';
    state<=yewrsn;
    else
    recount<='1';
    state<=rewgsn;
    sign_state<="001";
    end if;
    end if;
    when others=>
    state<=rewgsn;
    recount<='0';
    sign_state<="001";
    end case;
    end if;
    end if;
    end process;
    light<="010010" when (state=rewgsn) else
    "011000" when (state=rewysn) else
    "100001" when (state=gewrsn) else
    "100100" when (state=yewrsn) else
    "110000";
    red<=light(5 downto 4);
    yellow<=light(3 downto 2);
    green<=light(1 downto 0);
    end;
    5.系统的VHDL程序如下:
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    entity light is
    port(reset:in std_logic;
    clk:in std_logic;
    a_m:in std_logic;
    st_butt:in std_logic;
    recount:out std_logic;
    next_state:out std_logic;
    sign_state:out std_logic_vector(2 downto 0);
    red:out std_logic_vector(1 downto 0);
    green:out std_logic_vector(1 downto 0);
    yellow:out std_logic_vector(1 downto 0);
    led:out std_logic_vector(24 downto 0));
    end;
    architecture bhv of light is
    signal ena_scan_1:std_logic;
    signal ena_1hz_1:std_logic;
    signal flash_1hz_1:std_logic;
    signal recount_1:std_logic;
    signal next_state_1:std_logic;
    signal sign_state_1:std_logic_vector(2 downto 0);
    signal load:std_logic_vector(7 downto 0);
    component shizhong
    port(reset:in std_logic;
    clk:in std_logic;
    ena_scan:out std_logic;
    ena_1hz:out std_logic;
    flash_1hz:out std_logic);
    end component;
    component jishu
    port(reset:in std_logic;
    clk:in std_logic;
    ena_scan:in std_logic;
    recount:in std_logic;
    sign_state:in std_logic_vector(2 downto 0);
    load:out std_logic_vector(7 downto 0));
    end component;
    component daojishi
    port(reset:in std_logic;
    clk:in std_logic;
    ena_1hz:in std_logic;
    recount:in std_logic;
    load:in std_logic_vector(7 downto 0);
    led:out std_logic_vector(24 downto 0);
    next_state:out std_logic);
    end component;
    component honglvdeng
    port(reset:in std_logic;
    clk:in std_logic;
    ena_scan:in std_logic;
    ena_1hz:in std_logic;
    flash_1hz:in std_logic;
    a_m:in std_logic;
    st_butt:in std_logic;
    next_state:in std_logic;
    recount:out std_logic;
    sign_state:out std_logic_vector(2 downto 0);
    red:out std_logic_vector(1 downto 0);
    green:out std_logic_vector(1 downto 0);
    yellow:out std_logic_vector(1 downto 0));
    end component;
    begin
    u1:shizhong port map(reset,clk,ena_scan_1,ena_1hz_1,flash_1hz_1);
    u2:jishu port map(reset,clk,ena_scan_1,recount_1,sign_state_1,load);
    u3:daojishi port map(reset,clk,ena_1hz_1,recount_1,load,next_state_1);
    u4:honglvdeng port map(reset,clk,ena_scan_1,ena_1hz_1,flash_1hz_1,a_m,st_butt,next_state_1,recount_1,sign_state_1,red,green,yellow);
    next_state<=next_state_1;
    recount<=recount_1;
    sign_state<=sign_state_1;
    end;

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