verilog代码，谁能看懂，貌似挺常用的？

always@(posedge clk_out_0, negedge reset_n) begin
if(reset_n == 1'b0)
current_state <= idle;
else
current_state <= next_state;
end

always@(*) begin
next_state = current_state;
case(current_state)
idle:begin
if(flaga == 1'b1)
else
next_state = idle;
end
if(flaga == 1'b0)
next_state = idle;
else
end
default:
next_state = idle;
end

6个回答

always@(posedge clk_out_0, negedge reset_n) begin //循环，一旦clk_out_0有上升沿或reset_n下降沿就使用begin下语句
//下降沿：变到0
//上升沿：变到1
if(reset_n == 1'b0) //判断 reset_n==一个单位的 0
current_state <= idle; //不等待把 current_state=idle
//=直接赋值
//<=不等待赋值
// a=b;b=c;c=d;顺序是从a到c
//a<=b;b<=c;c<=d;不知顺序，因为哪个先都是不知
else
current_state <= next_state; //从这知道他是状态的，每个状态一个，是摩尔类（不在意我说的这个，这个没关系）
end //停，不是停下程序，是循环，就是结束循环

always@(*) begin //有变化，循环
next_state = current_state; //把这个状态放下状态，这个是逆循环
idle:begin
if(flaga == 1'b1) //判断

else
next_state = idle;
end
if(flaga == 1'b0)
next_state = idle;
else
end
default:
next_state = idle;
end //结束

always@(posedge clk or negedge reset) begin ... end是在描述F.F的電路(序向邏輯)