verilog代码，谁能看懂，貌似挺常用的？

Question

always@(posedge clk_out_0, negedge reset_n) begin
if(reset_n == 1'b0)
current_state <= idle;
else
current_state <= next_state;
end

always@(*) begin
next_state = current_state;
case(current_state)
idle:begin
if(flaga == 1'b1)
next_state = read;
else
next_state = idle;
end
read:begin
if(flaga == 1'b0)
next_state = idle;
else
next_state = read;
end
default:
next_state = idle;
end

Answer 1

已经懂了，这是典型的三段式状态机，具体的可以去百度，帖子就这样结了，此外给二楼点辛苦分把，诶，好像不行啊，