错误如下:
Error (10839): Verilog HDL error at TEST.v(26): using implicit port connections is a SystemVerilog feature
代码如下:
module TEST
(
phase_a,
phase_b,
dq,
);
input phase_a;
input phase_b;
inout [15:0] dq;
DECODER(
.reset(reset),
.enable(enable),
.phase_a(phase_a),
.phase_b(phase_b),
.counter(counter)
);
RAM(
.dq(dq),
.address(address),
.n_e(n_e),
.n_w(n_w),
.output_enable
);
endmodule