//顶层模块
module kongzhi(clk,rst,s1,s2,s3,s4,s5,display,seg_bit,spk,led_test,hour_test,min_test,naozhong_test,
hsync,vsync,vga_rgb);
input clk;
input rst,s1,s2,s3,s4,s5;
output spk;
output naozhong_test;
wire sech;
wire sec1;
wire minh,min1,hour1,hourh;
output hour_test;
output min_test;
output led_test;
output [6:0]display;
output [3:0]seg_bit;
output hsync;
output vsync;
output[7:0]vga_rgb;
shizhong instance_name (
.clk(clk),
.rst(rst),
.s1(s1),
.s2(s2),
.s3(s3),
.s4(s4),
.s5(s5),
.display(display),
.seg_bit(seg_bit),
.spk(spk),
.led_test(led_test),
.hour_test(hour_test),
.min_test(min_test),
.naozhong_test(naozhong_test),
.sec1(sec1),
.sech(sech),
.minh(minh),
.min1(min1),
.hourh(hourh),
.hour1(hour1)
);
vga_rgb nstance_name (
.clk(clk),
.rst(rst),
.hsync(hsync),
.vsync(vsync),
.vga_rgb(vga_rgb),
.hourh(hourh),
.hour1(hour1),
.minh(minh),
.min1(min1),
.sech(sech),
.sec1(sec1)
);
endmodule
//时钟模块
module shizhong(clk,rst,s1,s2,s3,s4,s5,display,seg_bit,spk,led_test,hour_test,min_test,naozhong_test,sec1,sech,minh,min1,hourh,hour1);
input clk;
input rst,s1,s2,s3,s4,s5; //1234实现小时分钟加减1，5闹钟功能是否开启
output reg spk;//闹钟灯
output reg naozhong_test;//闹钟功能开启灯亮
output reg [7:0]sech;
output reg [7:0]sec1;
output reg[7:0] minh,min1,hour1,hourh;
output reg hour_test;//时钟调整灯亮
output reg min_test;//分钟调整灯亮
reg clk_1hz;//秒脉冲
reg clk_1khz;//动态扫描脉冲
output reg led_test;//测试灯
output reg[6:0]display;//是吗管
output reg[3:0]seg_bit;//位选通
reg[30:0]clk_count1;
reg[20:0]counter;
// reg[7:0]secl,sech;
//reg[7:0]minl,minh;
//reg[7:0]hourl,hourh;
reg[7:0]disp_temp; //数字1-9
reg[3:0]state;
initial
begin
display<=7'bz;state<=0;
counter<=0;
clk_count1<=0;
sec1<=6;
sech<=3;
min1<=9;
minh<=5;
hour1<=3;
hourh<=2;
end
always@(posedge clk)
begin
if(clk_count1>=25_000_000)
begin
clk_count1<=0;
clk_1hz<=~clk_1hz;
end
else clk_count1<=clk_count1+1; //分频得到秒脉冲
if(counter>=125000)
begin
counter<=0;
clk_1khz<=~clk_1khz;
end
else
counter<=counter+1;//分频得到动态扫描脉冲
case(disp_temp)
0:display<=7'b100_0000;
1:display<=7'b111_1001;
2:display<=7'b010_0100;
3:display<=7'b011_0000;
4:display<=7'b001_1001;
5:display<=7'b001_0010;
6:display<=7'b000_0010;
7:display<=7'b111_1000;
8:display<=7'b000_0000;
9:display<=7'b001_0000;
default:display<=7'bz;
endcase
end
always@(posedge clk_1hz )
if(!rst) //复位信号初始化0000
begin
sec1=0;
sech=0;
min1=0;
minh=0;
hour1=0;
hourh=0;
end
else
begin
if(!s1)//实现小时个位+1
begin
if(hour1==9)
begin
hour1=0;
hourh=hourh+1;
end
else
begin
if(hourh==2&&hour1==3)
begin
hourh=0;
hour1=0;
end
else
hour1=hour1+1;
end
end
else
if(!s2) //实现分钟个位加1
begin
if(min1==9)
begin
min1=0;
if(minh==5)
minh=0;
else
minh=minh+1;
end
else min1=min1+1;
end
else
if(!s3) //实现小时个位减1
begin
if(hourh==0&&hour1==0)
begin
hourh=2;
hour1=3;
end
else
if(hour1==0)
begin
hour1=9;
hourh=hourh-1;
end
else
hour1=hour1-1;
end
else
if(!s4) //实现分钟减1
begin
if(minh==0&&min1==0)
begin
minh=5;
min1=9;
end
else
if(min1==0)
begin
min1=9;
minh=minh-1;
end
else
min1=min1-1;
end
else //计时功能
begin
sec1=sec1+1;
if(sec1==10)
begin
sec1=0;
sech=sech+1;
end
if(sech==6)
begin
sech=0;
min1=min1+1;
end
if(min1==10)
begin
min1=0;
minh=minh+1;
end
if(minh==6)
begin
minh=0;
hour1=hour1+1;
end
if(hour1==10)
begin
hour1=0;
hourh=hourh+1;
end
if(hourh==2&&hour1==4)
begin
hourh=0;
hour1=0;
end
end
end
always@(posedge clk_1khz) begin
case(s5)//闹钟功能开启
1:begin
naozhong_test=1;//闹钟功能开启灯亮
if(minh==0&&min1==0&&sec1%2==0)//闹钟时间设定
spk=1;//到点闹钟灯亮
end
0:begin spk=0;
naozhong_test=0;
end
default begin
end
endcase
if(s1==0||s3==0)//小时改变则灯亮
hour_test<=!hour_test;
else
hour_test<=0;
if(s2==0||s4==0)//分钟改变则灯亮
min_test<=!min_test;
else
min_test<=0;
end
always@(posedge clk_1khz)
begin
case(state)
0:begin seg_bit<=4'b0111;
disp_temp<=min1;
state<=1;
led_test=1;
end
1:begin seg_bit<=4'b1011;
disp_temp<=minh;
state<=2;
led_test=1;
end
2:begin seg_bit<=4'b1101;
disp_temp<=hour1;
state<=3;
led_test=~clk_1hz;
end
3:begin seg_bit<=4'b1110;
disp_temp<=hourh;
state<=0;
led_test=1;
end
default:begin display<=7'bz;
state<=0;
end
endcase
end
endmodule
//vga模块
module vga_rgb(clk,rst,hsync,vsync,vga_rgb,hourh,hour1,minh,min1,sech,sec1
);
input clk;
input rst;
output hsync;
output vsync;
output[7:0]vga_rgb;
wire [15:0]rom_data;
output hourh,hour1,minh,min1,sech,sec1;
reg[11:0]x_cnt;
reg[9:0]y_cnt;
reg[7:0]sec1,sech;
reg[7:0]min1,minh;
reg[7:0]hour1,hourh;
// output [2:0] vga_r;
//output [2:0]vga_g;
//reg[2:0]vga_r,vga_g;
//output[1:0]vga_b;
//reg[1:0]vga_b;
always@(posedge clk or negedge rst)//行计数器记满一行清零
if(!rst)x_cnt<=12'd0;
else if(x_cnt==12'd1039)x_cnt<=12'd0;
else x_cnt<=x_cnt+1'b1;
always@(posedge clk or negedge rst)//记满一行，场计数器加一，场计数器记满687行，清零 完成一针
if(!rst)y_cnt<=10'd0;
else if(y_cnt==10'd687)y_cnt<=10'd0;
else if(x_cnt==12'd1039)y_cnt<=y_cnt+1'b1;
reg hsync,vsync;
always@(posedge clk or negedge rst)//产生行同步型号，记满一行有120个时钟周期的低脉冲出现
if(!rst) hsync<=1'b1;
else if(x_cnt==0)hsync<=1'b0;
else if(x_cnt==12'd120)hsync<=1'b1;
always@(posedge clk or negedge rst)//产生场同步信号，记满一个场后，游6个行的时间出现低脉冲
if(!rst) vsync<=1'b1;
else if(y_cnt==10'd0)vsync<=1'b0;
else if(y_cnt==10'd6)vsync<=1'b1;
//reg[15:0]rom_data
reg[3:0]a;
reg[11:0]rom_addr;
wire[7:0]vga_rgb;
wire kong,sec_shi,sec_ge,minu_shi,minu_ge,hour_shi,hour_ge,maohao;
reg mode_xuanze;
always@(posedge clk) begin
if(y_cnt>= 300 && y_cnt <= 331)
begin
rom_addr = y_cnt - 300;
if(x_cnt>= 176 && x_cnt <= 191 ) begin
mode_xuanze = hour_shi;
a = 191-x_cnt; end
else if(x_cnt>= 192 &&x_cnt <= 207 ) begin
mode_xuanze = kong;
a = 207-x_cnt; end
else if(x_cnt >= 208 && x_cnt <= 223 ) begin
mode_xuanze = maohao;
a = 223-x_cnt; end
else if(x_cnt >= 224 && x_cnt <= 239 ) begin
mode_xuanze = minu_shi;
a = 239-x_cnt; end
else if(x_cnt >= 240 && x_cnt <= 255 ) begin
mode_xuanze = kong;
a= 255-x_cnt; end
else if(x_cnt >= 256 && x_cnt <= 271 ) begin
mode_xuanze = minu_ge;
a = 271-x_cnt; end
else if(x_cnt>= 272 && x_cnt <= 287 ) begin
mode_xuanze = kong;
a = 287-x_cnt; end
else if(x_cnt >= 288 && x_cnt <= 303 ) begin
mode_xuanze = sec_shi;
a = 303-x_cnt; end
else if(x_cnt >= 304 && x_cnt <= 319 ) begin
mode_xuanze = kong;
a = 319-x_cnt; end
else if(x_cnt >= 320 && x_cnt <= 335 ) begin
mode_xuanze = sec_ge;
a =335-x_cnt ; end
else begin
mode_xuanze = kong;
a = 0; end
end
else
begin
mode_xuanze = kong;
a = 0;
rom_addr = 0;
end
end
reg [3:0] data_time;
always@(posedge clk) begin
case(mode_xuanze)
hour_shi:
data_time =hourh;
hour_ge:
data_time = hour1;
minu_shi :
data_time = minh;
minu_ge :
data_time = min1;
sec_shi :
data_time = sech;
sec_ge :
data_time = sec1;
maohao :
data_time = 10;
kong :
data_time = 11;
default:
data_time = 11;
endcase
end
reg [8:0] address_base;
always@(posedge clk)
begin
case(data_time)
4'd0 :
address_base = 0;
4'd1 :
address_base = 16;
4'd2 :
address_base = 32;
4'd3 :
address_base = 48;
4'd4 :
address_base = 64;
4'd5 :
address_base = 80;
4'd6 :
address_base = 96;
4'd7 :
address_base = 112;
4'd8 :
address_base = 128;
4'd9 :
address_base = 144;
4'd10:
address_base = 176;
4'd11:
address_base = 192;
default:
address_base =192;
endcase
end
wire [8:0] addra;
assign addra = address_base + rom_addr;
// reg[15:0]rom_data
//assign vga_rgb = rom_data[a]?111_000_00:000_000_00;
bga your_instance_name (
.clka(clk), // input clka
.addra(addra), // input [7 : 0] addra
.douta(rom_data) // output [15 : 0] douta
);
assign vga_rgb = rom_data[a]?111_000_00:000_000_00;
endmodule
