我现在做的事用verilog程序编一个图像文件，然后传给图像采集卡，通过NI 图像文件生成器来采集图片。其中图片是80*120大小的，在NI图像文件生成器采集的时候出现错误。
错误是：cannot detect valid timing signals.Make sure the camera is turned on ,outputing video (not waiting for a trigger),and connected correctly.
想问下有没有知道这个是什么原因造成的。我的代码是：
`timescale 1ns / 1ps
module vga1(
input wire clk,
input wire clr,
output reg hsync, //行同步
output reg vsync,
output reg [9:0] vc,
output reg [9:0] hc, // 列同步
output reg [15:0]dataout
);
reg [15:0]data;
reg vsenable; //Enbale for the Vertical counter
reg clk50m;
// 行计数器
//reg [9:0] vc; // 列计数器
//50mhz时钟的产生
always@(posedge clk)
if(clr)
clk50m<=0;
else clk50m<=~clk50m;
//数据产生
always@(posedge clk50m or posedge clr)
begin
if(clr==1)
data<=16'b1010_1001_1101_1010;
else data<=~data;
end
//行同步信号计数器
always@(posedge clk50m or posedge clr )
begin
if(clr==1)
hc<=0;
else
begin
if(hc==10'd150) //如果hc记到一行+延时110个时钟周期
begin
//The counter has reached the end of pixel count
hc<=0; //计数器复位
vsenable<=1; //列计数器开始计数
//Enable the vertical counter to increment
end
else
begin
hc<=hc+1; //Increment the horizontal counter
vsenable<=0; //Leave the vsenable off
end
end
end
//产生hsync脉冲 行同步脉冲
always@(posedge clk50m)
begin
if ((hc>=1)&&(hc<10'd41))
hsync=1;
else
hsync=0;
end
//场同步信号计数器
always@(posedge clk50m or posedge clr)
begin
if(clr==1)
vc<=0;
else
if(vsenable==1)
begin
if(vc==10'd119) //所有的行都输出了
//Reset when the number of lines is reached
vc<=0;
else
vc<=vc+1;
//场计数器加1
end
end
//产生vsync脉冲 帧同步脉冲
always@(posedge clk50m or posedge clr )//加了行同步的下降沿控制
if(clr)
vsync<=0;
else if(hsync==0&&vc==10'd119) //只有在行下降沿才产生帧0
vsync<=0;
else if(hsync)
vsync<=1;
//Enable video out when within the porches
always@(posedge clk50m)
begin
if(hsync)
dataout<=data;
else
dataout<=0;
end
endmodule
