FPGA新手提问,verilog程序中多次例化同一个module,在顶层module中多次例化的module是并行执行还是串行执行的?
```ad7606 u1_ad7606
(
//Input ports
.sysclk (sysclk),
.ad_DB (ad_DB_1),
.busy (ad_busy_1),
.RST_B (reset_b),
//Output ports
.cva_cvb (ad_cva_cvb_1),
.rd (ad_rd_1),
.cs (ad_cs_1),
.rst (ad_rst_1),
.ad_DATA (ad_DATA_1)
);
ad7606 u2_ad7606
(
//Input ports
.sysclk (sysclk),
.ad_DB (ad_DB_2),
.busy (ad_busy_2),
.RST_B (reset_b),
//Output ports
.cva_cvb (ad_cva_cvb_2),
.rd (ad_rd_2),
.cs (ad_cs_2),
.rst (ad_rst_2),
.ad_DATA (ad_DATA_2)
);