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2017-05-03 03:44 阅读 2.6k

求DDS产生方波verilog代码

1

一些资料都是任意波形产生需要用到ROM及滤波,我想要一个不用ROM和滤波模块的只产生方波的采用DDS产生方波的verilog代码

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2条回答 默认 最新

  • morgerton 白萝卜blb 2017-05-03 05:32
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  • qimoDIY 起魔 2019-08-31 05:14

    你要产生的是50%的方波呢?还是PWM波呢?还是PDM波呢?

    module square_wave(
        input clk,
        input rst,
    
        // control port
        // high_period must be less than period, defined as the length of 1 in one period
        input      [15:0] period,
        input      [15:0] high_period,
        output reg        wave_out
    );
    
    reg [15:0] period_count;
    always @(posedge clk or posedge rst) begin
        if(rst) begin
            period_count <= 16'd0;
            wave_out <= 1'b1;
        end
        else if(period_count < period) begin
            period_count <= period_count + 16'd1;
            wave_out <= (period_count < high_period) ? 1'b1 : 1'b0;
        end
    end
    
    endmodule
    
    
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