`timescale 1s / 1ms
module ledtest2(led1
);
output[2:0] led1;
reg[2:0] le;
initial
begin
le=3'b001;//红灯
#3 le=3'b010;//绿灯
end
assign led1=le;
endmodule
`timescale 1s / 1ms
module ledtest2(led1
);
output[2:0] led1;
reg[2:0] le;
initial
begin
le=3'b001;//红灯
#3 le=3'b010;//绿灯
end
assign led1=le;
endmodule