shuang1994
太上无情
2017-07-06 01:51

为什么能综合能仿真但不能生成流文件

  • verilog mips vivado

module ledtest2(led);
output led;
wire led;
reg clk;

initial
begin
clk=0;
end

always
begin
#2 clk=~clk;
end
assign led=clk;
endmodule

生成流文件时老是报错:
[Drc 23-20] Rule violation (LUTLP-1) Combinatorial Loop - 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. To allow bitstream creation for designs with combinatorial logic loops (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. led_OBUF_inst_i_1.

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