在配置STM32F103C8T6 +nrf2401问题时,SPI读写功能没问题,即nrf2401 check成功。
我配置发送端关闭自动应答:SPI_RW_Reg(NRF_WRITE_REG + EN_AA, 0x00); // Enable Auto.Ack:Pipe0
发送完成后,读取status寄存器内容为0x2e, fifostatus寄存器内容为0x11,即表示发送模块成功发送。
我配置接收端关闭ACK: SPI_RW_Reg(NRF_WRITE_REG + EN_AA, 0x00); // Enable Auto.Ack:Pipe0,在上述发送端一直工作前提下接收端不能接收数据,查看
接收端status寄存器内容为:0x0e,表示接收端未收到数据。
我猜想不能通行原因是通道、地址、频率、模式不正确,但仔细检查发送、接收端上述配置完全一样。现在不知道问题出在哪里了,请各位帮我看看。
uint8_t NRF24L01_Check(void)
{
uint8_t buf[5]={0XA5,0XA5,0XA5,0XA5,0XA5};
uint8_t i;
SPI_Write_Buf(NRF_WRITE_REG+TX_ADDR,buf,5);//
SPI_Read_Buf(TX_ADDR,buf,5);
for(i=0;i<5;i++)if(buf[i]!=0XA5)break;
if(i!=5)return 1;
return 0;
}
void TX_Mode(void)
{
NRF24L01_SCK_L;
NRF24L01_CE_L;
SPI_Write_Buf(NRF_WRITE_REG + TX_ADDR, (u8*)TX_ADDRESS, 5);
SPI_Write_Buf(NRF_WRITE_REG + RX_ADDR_P0, (u8*)TX_ADDRESS, 5);
SPI_RW_Reg(NRF_WRITE_REG + EN_AA, 0x00); // Enable Auto.Ack:Pipe0
SPI_RW_Reg(NRF_WRITE_REG + EN_RXADDR, 0x00); // Enable Pipe0
SPI_RW_Reg(NRF_WRITE_REG + SETUP_RETR, 0x00);
SPI_RW_Reg(NRF_WRITE_REG + SETUP_AW, 0x03);
SPI_RW_Reg(NRF_WRITE_REG + RF_CH, 40);
SPI_RW_Reg(NRF_WRITE_REG + RF_SETUP, 0x0F);
SPI_RW_Reg(NRF_WRITE_REG + RX_PW_P0, TX_PLOAD_WIDTH);
SPI_RW_Reg(NRF_WRITE_REG + CONFIG, 0x0e);
NRF24L01_CE_H;
delay_us(150);
}
void RX_Mode(void)
{
NRF24L01_SCK_L;
NRF24L01_CE_L;
SPI_Write_Buf(NRF_WRITE_REG + RX_ADDR_P0, (u8*)TX_ADDRESS, TX_ADR_WIDTH); // Use the same address on the RX device as the TX device
SPI_RW_Reg(NRF_WRITE_REG + EN_AA, 0x00); // Enable Auto.Ack:Pipe0
SPI_RW_Reg(NRF_WRITE_REG + EN_RXADDR, 0x01); // Enable Pipe0
SPI_RW_Reg(NRF_WRITE_REG + SETUP_AW, 0x03); //
SPI_RW_Reg(NRF_WRITE_REG + RF_CH, 40); // Select RF channel 40
SPI_RW_Reg(NRF_WRITE_REG + RX_PW_P0, TX_PLOAD_WIDTH);
SPI_RW_Reg(NRF_WRITE_REG + RF_SETUP, 0x0f);
SPI_RW_Reg(NRF_WRITE_REG + CONFIG, 0x0f);
NRF24L01_CE_H; //
delay_us(150);
}
u8 NRF24L01_RxPacket(u8 *rx_buf)
{
int16_t sta,fifosta,tt=0;
sta=SPI_Read_Reg(STATUS);
fifosta=SPI_Read_Reg(FIFO_STATUS);
if(!( NRF24L01_IRQ))
{
sta=SPI_Read_Reg(STATUS);
if(sta&RX_OK)
{
SPI_Read_Buf(RD_RX_PLOAD,rx_buf,RX_PLOAD_WIDTH);
SPI_RW_Reg(FLUSH_RX,0xff);
SPI_RW_Reg(NRF_WRITE_REG+STATUS,0x7f);
tt=1;
}
}
return (tt);
}
u8 NRF24L01_TxPacket(u8 *txbuf)
{
uint8_t sta,fifosta,cd;
NRF24L01_CE_L;
SPI_Write_Buf(WR_TX_PLOAD,txbuf,TX_PLOAD_WIDTH);
sta = SPI_Read_Reg(STATUS);
fifosta = SPI_Read_Reg(FIFO_STATUS);
NRF24L01_CE_H;//
while(NRF24L01_IRQ!=0);//
sta=SPI_Read_Reg(STATUS); //
fifosta = SPI_Read_Reg(FIFO_STATUS);
cd=SPI_Read_Reg(0x09);
SPI_RW_Reg(NRF_WRITE_REG+STATUS,sta);
if(sta&MAX_TX)//
{
SPI_RW_Reg(FLUSH_TX,0xff);//
return MAX_TX;
}
if(sta&TX_OK)
{
;
return 0x01;
}
return 0xff;//
}