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RLHaides
2017-11-28 11:51
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verilog basys3 计数器设计

想做一个计数器, 当控制端mode为0时, 计数器由1至12递增, 当控制端mode为1时, 计数器由12至1递减, 同时将数字用basys3板上的数码管显示(利用扫描)
可是在basys3板上, 数码管运行停滞在03
代码如下

 `timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2017/11/28 08:42:53
// Design Name: 
// Module Name: dis
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module dis(
    input clk,
    input mode,
    output reg[3:0] data,
    output reg[10:0] seg
    );
    reg [4:0] count = 1;
    reg[20:0] number = 0;
    reg[20:0] number2 = 0;
    reg[2:0] sig = 0;
    reg[10:0] temp1;
    reg[10:0] temp2;

    always@(posedge clk)
    begin
       if (count == 1)
       begin
          data = 4'b0001;
            temp1= 11'b11101001111;
            temp2 = 11'b11010000001;
       end  
       if (count == 2)
       begin
          data = 4'b0010;

          temp1 = 11'b11100010010;
          temp2 = 11'b11010000001;


       end
       if (count == 3)
       begin
          data = 4'b0011;

          temp1 = 11'b11100000110;
          temp2 = 11'b11010000001;

       end
       if (count == 4)
       begin
          data = 4'b0100;
          temp1= 11'b11101001100;
          temp2 = 11'b11010000001;

       end
       if (count == 5)
       begin
           data = 4'b0101;
           temp1 = 11'b11100100100;
           temp2 = 11'b11010000001;

       end
       if (count == 6)
       begin
           data = 4'b0110;
           temp1 = 11'b11100100000;
           temp2= 11'b11010000001;
       end
       if (count == 7)
       begin
           data = 4'b0111;
           temp1= 11'b11100001111;
          temp2 = 11'b11010000001;
       end
       if (count == 8)
       begin
           data = 4'b1000;
           temp1= 11'b11100000000;
          temp2= 11'b11010000001;
       end
       if (count == 9)
       begin
           data = 4'b1001;
           temp1= 11'b11100000100;
           temp2 = 11'b11010000001;
       end
       if (count == 10)
       begin
           data = 4'b1010;
           temp1 = 11'b11100000001;
          temp2 = 11'b11011001111;
       end
       if (count == 11)
       begin
           data = 4'b1011;
           temp1 = 11'b11101001111;
          temp2 = 11'b11011001111;
       end
       if (count == 12)
       begin
           data = 4'b1100;
           temp1= 11'b11100010010;
           temp2 = 11'b11011001111;
       end                                                 
    end
    always@(posedge clk)
    begin
       number = number + 1;
       number2 = number2 + 1;
        if (number2 == 100000)
                begin
                    seg = temp1;  
                end
    if (number2 == 200000)
                             begin
                                 seg = temp2;
                                 number2 = 0;  
                             end             
       if (number == 10000000)
       begin
          number = 0;
          count = count + 1;
       end
       if (mode == 0)
       begin
          count = (count ) % 12 + 1;
       end
       if (mode == 1)
       begin
          if (count == 1)
              count = 12;
          else
              count = count - 1;
       end
    end
endmodule


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1条回答 默认 最新

  • demonprime
    demonprime 2018-01-18 03:59
    已采纳
       if (number == 10000000)
       begin
          number = 0;
          count = count + 1;
       end
       if (mode == 0)
       begin
          count = (count ) % 12 + 1;
       end
       if (mode == 1)
       begin
          if (count == 1)
              count = 12;
          else
              count = count - 1;
       end
    end
        你本意是计数到10000000再加count吧?这段代码错了,count每个时钟周期都会加1或减一,高频情况下数码管显示不可能正确的;
    
        另外给个建议,边沿触发的always块用非阻塞赋值,阻塞赋值会增加大量的逻辑并且导致critical path变长,以及,像你这样的错误也不容易检查出来。
    
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