Verilog锁存器,锁存6组数据后为什么读取时第一组数据为什么是锁存的第二组数据? 5C

/* en为使能端,get为锁存/显示数据按键,rst为置零按键 */
module suocun(

en,get,rst,
s1_1,s2_1,s3_1,s1_2,s2_2,s3_2,

key,
n1_1,n2_1,n3_1,n1_2,n2_2,n3_2

);

input en,get,rst;
input [3:0] s1_1,s2_1,s3_1,s1_2,s2_2,s3_2;

output reg key;
output reg[3:0] n1_1,n2_1,n3_1,n1_2,n2_2,n3_2;

reg[2:0] cnt1;
reg[2:0] cnt2;

reg[3:0] data1_1_1,data1_1_2,data1_2_1,data1_2_2,data1_3_1,data1_3_2;
reg[3:0] data2_1_1,data2_1_2,data2_2_1,data2_2_2,data2_3_1,data2_3_2;
reg[3:0] data3_1_1,data3_1_2,data3_2_1,data3_2_2,data3_3_1,data3_3_2;
reg[3:0] data4_1_1,data4_1_2,data4_2_1,data4_2_2,data4_3_1,data4_3_2;
reg[3:0] data5_1_1,data5_1_2,data5_2_1,data5_2_2,data5_3_1,data5_3_2;
reg[3:0] data6_1_1,data6_1_2,data6_2_1,data6_2_2,data6_3_1,data6_3_2;

always @(posedge get or negedge rst)
begin
if(!rst)
begin
cnt1<=3'd0;
cnt2<=3'd0;
end
else
begin
if(en)
begin
if(cnt1==3'd7)
cnt1<=3'd0;
else
cnt1<=cnt1+1'b1;
end
else
begin
if(cnt2==3'd7)
cnt2<=3'd0;
else
cnt2<=cnt2+1'b1;
end
end
end

always @(*)
begin
if(!rst)
begin
data1_1_1<=0;data1_1_2<=0;data1_2_1<=0;data1_2_2<=0;data1_3_1<=0;data1_3_2<=0;
data2_1_1<=0;data2_1_2<=0;data2_2_1<=0;data2_2_2<=0;data2_3_1<=0;data2_3_2<=0;
data3_1_1<=0;data3_1_2<=0;data3_2_1<=0;data3_2_2<=0;data3_3_1<=0;data3_3_2<=0;
data4_1_1<=0;data4_1_2<=0;data4_2_1<=0;data4_2_2<=0;data4_3_1<=0;data4_3_2<=0;
data5_1_1<=0;data5_1_2<=0;data5_2_1<=0;data5_2_2<=0;data5_3_1<=0;data5_3_2<=0;
data6_1_1<=0;data6_1_2<=0;data6_2_1<=0;data6_2_2<=0;data6_3_1<=0;data6_3_2<=0;
end
else
begin
if(en)
begin
case(cnt1)
3'd1:
begin
data1_1_1<=s1_1;data1_1_2<=s1_2;data1_2_1<=s2_1;
data1_2_2<=s2_2;data1_3_1<=s3_1;data1_3_2<=s3_2;
end
3'd2:
begin
data2_1_1<=s1_1;data2_1_2<=s1_2;data2_2_1<=s2_1;
data2_2_2<=s2_2;data2_3_1<=s3_1;data2_3_2<=s3_2;
end
3'd3:
begin
data3_1_1<=s1_1;data3_1_2<=s1_2;data3_2_1<=s2_1;
data3_2_2<=s2_2;data3_3_1<=s3_1;data3_3_2<=s3_2;
end
3'd4:
begin
data4_1_1<=s1_1;data4_1_2<=s1_2;data4_2_1<=s2_1;
data4_2_2<=s2_2;data4_3_1<=s3_1;data4_3_2<=s3_2;
end
3'd5:
begin
data5_1_1<=s1_1;data5_1_2<=s1_2;data5_2_1<=s2_1;
data5_2_2<=s2_2;data5_3_1<=s3_1;data5_3_2<=s3_2;
end
3'd6:
begin
data6_1_1<=s1_1;data6_1_2<=s1_2;data6_2_1<=s2_1;
data6_2_2<=s2_2;data6_3_1<=s3_1;data6_3_2<=s3_2;
end
default: ;
endcase
end
end
end

always @(*)
begin
if(!en)
begin
case(cnt2)
3'd1:
begin
n1_1<=data1_1_1;n1_2<=data1_1_2;n2_1<=data1_2_1;
n2_2<=data1_2_2;n3_1<=data1_3_1;n3_2<=data1_3_2;
end
3'd2:
begin
n1_1<=data2_1_1;n1_2<=data2_1_2;n2_1<=data2_2_1;
n2_2<=data2_2_2;n3_1<=data2_3_1;n3_2<=data2_3_2;
end
3'd3:
begin
n1_1<=data3_1_1;n1_2<=data3_1_2;n2_1<=data3_2_1;
n2_2<=data3_2_2;n3_1<=data3_3_1;n3_2<=data3_3_2;
end
3'd4:
begin
n1_1<=data4_1_1;n1_2<=data4_1_2;n2_1<=data4_2_1;
n2_2<=data4_2_2;n3_1<=data4_3_1;n3_2<=data4_3_2;
end
3'd5:
begin
n1_1<=data5_1_1;n1_2<=data5_1_2;n2_1<=data5_2_1;
n2_2<=data5_2_2;n3_1<=data5_3_1;n3_2<=data5_3_2;
end
3'd6:
begin
n1_1<=data6_1_1;n1_2<=data5_1_2;n2_1<=data6_2_1;
n2_2<=data6_2_2;n3_1<=data5_3_1;n3_2<=data6_3_2;
end
default:
begin
n1_1<=s1_1;n1_2<=s1_2;n2_1<=s2_1;
n2_2<=s2_2;n3_1<=s3_1;n3_2<=s3_2;
end
endcase
end
else
begin
n1_1<=s1_1;n1_2<=s1_2;n2_1<=s2_1;
n2_2<=s2_2;n3_1<=s3_1;n3_2<=s3_2;
end
end

always @(*)
begin
if(cnt1==3'd5 || cnt2==3'd6)
key=1'd1;
else
key=1'd0;
end

endmodule

1个回答

Csdn user default icon
上传中...
上传图片
插入图片
抄袭、复制答案,以达到刷声望分或其他目的的行为,在CSDN问答是严格禁止的,一经发现立刻封号。是时候展现真正的技术了!
立即提问