weixin_39576294
weixin_39576294
2021-01-09 11:52

Added IAR Export RTOS CORTEX M3

Tested LPC1768 Basic thread example and it worked. I will add it for M0, M0+ and M4 as well in a later pull request.

该提问来源于开源项目:ARMmbed/mbed-os

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6条回答

  • weixin_39784972 weixin_39784972 3月前

    I think you need to leave the RAM section starting where it was. The NVIC code to modify the vector table assumes that it can use the start of memory in most cases. I checked the code for the LPC1768 (cmsis_nvic.c) and it like others had this define:

     C
    #define NVIC_RAM_VECTOR_ADDRESS   (0x10000000)  // Location of vectors in RAM
    

    So either this behavior needs to change, because it is rather fragile, or you need to leave the linker how it was.

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  • weixin_39946355 tomorrow-77 3月前

    What I am missing is the description for changes in LPC icf file and rt_CMSIS.c.

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  • weixin_39576294 weixin_39576294 3月前

    Regarding rt_CMSIS.c, the changes was done to copy how __CC_ARM had done it. Nothing odd in this file. The icf file caused the RTOS program to even disable the usb external disk functionality after reset. I will comeback with comments regarding NVIC.

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  • weixin_39576294 weixin_39576294 3月前

    The older icf file had a too small heap for the rtos basic example. Changed it to more resemble the standard linker file from IAR

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  • weixin_39946355 tomorrow-77 3月前

    Is this ready for merging? The NVIC comments?

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  • weixin_39576294 weixin_39576294 3月前

    Yes this is ready for merge. The vectortable now has space at the beginning of RAM.

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