--为什么下列程序在xie0的check_error不变为一,而在du0xiex立马为一?
LIBRAry ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity checkram1 is
port (
ram_ce : out std_logic ; --ram pian xuan,di you xiao
ram_we : out std_logic; --ram xie shi neng,di you xiao
ram_oe: out std_logic; --ram hu chu shi neng,di you xiao
ram_db : inout std_logic_vector(15 downto 0); --ram shu ju duan
ram_addr : out std_logic_vector (18 downto 0); --ram di zhi
ram_ub: out std_logic;ram_lb: out std_logic;
checkram_ce : in std_logic ;
clk_50m : in std_logic ;
check_error : out std_logic :='1' ;
check_over: out std_logic :='1'
);
end checkram1;
architecture Behavioral of checkram1 is
signal ram_db_in : std_logic_vector(15 downto 0);
signal ram_db_out : std_logic_vector(15 downto 0);
signal ram_db_io : std_logic ; --ram_db输入输出控制，1输出，0输入
signal addr :std_logic_vector (18 downto 0) :="0000000000000000000"; --地址变量--
type states is (xie0,du0xiex,dux,dengdai); --状态类型
signal state :states := dengdai; --当前状态
signal timeofxie0 : std_logic_vector (7 downto 0) :="00000000"; --xie0计时标记
signal timeofdu0xiex : std_logic_vector (7 downto 0) :="00000000";--du0xiex计时标记
signal timeofdux : std_logic_vector (7 downto 0) :="00000000";--dux计时标记
begin
-- process (clk_50m,ram_db_io,ram_db_out)
-- begin
-- if (ram_db_io = '1' ) then
-- ram_db <= ram_db_out;
-- else ram_db <= (others=>'Z');
-- end if;
-- end process ;
--ram_db <= ram_db_out when ram_db_io ='1' else "ZZZZZZZZZZZZZZZZ";
process (clk_50m)
begin
if rising_edge(clk_50m) then
case state is
when dengdai =>
ram_addr <=(others =>'Z'); ram_db <=(others =>'Z');
ram_ce <='1';ram_oe <='1';ram_we <='1';
if checkram_ce = '0' then addr <= "0000000000000000000";state <= dengdai;
else addr <= "0000000000000000000"; state <= xie0;check_error <= '1';check_over <= '1';end if;
when xie0 =>
case timeofxie0 is
when "00000000"=> ram_db<="0000000000000001";ram_addr <=addr;
ram_db_io <= '1';
ram_ce<='0';ram_we<='1';ram_oe<='1';state<=xie0;
when "00000001"=> ram_ce<='0';ram_we<='0';ram_oe<='1';state<=xie0;
when "00000011"=> ram_ce<='0';ram_we<='1';ram_oe<='1';state<=xie0;
when "00001000"=> ram_addr <= addr;ram_ce<='0';ram_we<='1';ram_oe<='1';ram_db_io <= '0';state<=xie0;
when "00001001"=> ram_ce<='0';ram_we<='1';ram_oe<='0';state<=xie0;
when "00001011"=> ram_db_in <= ram_db; state<=xie0;
when "00001100"=> ram_ce<='0';ram_we<='1';ram_oe<='1'; state<=xie0;
when "01000000"=> if ram_db_in /= "0000000000000001" then
check_error <= '0';end if;
when "01010000"=> if addr="1111111111111111111" then
addr<="0000000000000000000";state <= du0xiex;
else addr<=addr+1;end if;
when others => state <= xie0;
end case;
when du0xiex =>
case timeofdu0xiex is
when "00000000"=> ram_addr <= addr;ram_ce<='0';ram_we<='1';ram_oe<='1';ram_db_io <= '0';state<=du0xiex;
when "00000001"=> ram_ce<='0';ram_we<='1';ram_oe<='0';state<=du0xiex;
when "00000011"=> ram_db_in <= ram_db; state<=du0xiex;
when "00000100"=> ram_ce<='0';ram_we<='1';ram_oe<='1'; state<=du0xiex;
when "01010000"=> if ram_db_in /= "0000000000000000" then
check_error <= '0';end if;
when "01010001"=> ram_db<=addr(15 downto 0);ram_addr <=addr;
ram_db_io <= '1';
ram_ce<='0';ram_we<='1';ram_oe<='1';state<=du0xiex;
when "01010010"=> ram_ce<='0';ram_we<='0';ram_oe<='1';state<=du0xiex;
when "01010100"=> ram_ce<='0';ram_we<='1';ram_oe<='1';state<=du0xiex;
when "10100001"=> if addr="1111111111111111111" then
addr<="1111111111111111111";state <= dux;
else addr<=addr+1;end if;
when others => state <= du0xiex;
end case;
when dux =>
case timeofdux is
when "00000000"=> ram_addr <= addr;ram_ce<='0';ram_we<='1';ram_oe<='1';ram_db_io <= '0';state<=dux;
when "00000001"=> ram_ce<='0';ram_we<='1';ram_oe<='0';state<=dux;
when "00000011"=> ram_db_in <= ram_db; state<=dux;
when "00000100"=> ram_ce<='0';ram_we<='1';ram_oe<='1'; state<=dux;
when "01010000"=> if ram_db_in /= addr then
check_error <= '0';end if;
when "01010001"=> if addr="0000000000000000000" then
addr<="0000000000000000000";state <= dengdai;check_over <= '0';
else addr<=addr-1;end if;
when others => state <= dux;
end case;
end case;
end if;
end process;
xie0jishi:process (clk_50m)
begin
if rising_edge(clk_50m) then
if state = xie0 then
if timeofxie0 = "01010000" then
timeofxie0 <="00000000";
else timeofxie0 <= timeofxie0 + 1;
end if;
else timeofxie0<= "00000000";
end if;
end if;
end process xie0jishi;
du0xiexjishi:process (clk_50m)
begin
if rising_edge(clk_50m) then
if state = du0xiex then
if timeofdu0xiex = "10100001" then
timeofdu0xiex <="00000000";
else timeofdu0xiex <= timeofdu0xiex + 1;
end if;
else timeofdu0xiex<= "00000000";
end if;
end if;
end process du0xiexjishi;
duxjishi:process (clk_50m)
begin
if rising_edge(clk_50m) then
if state = dux then
if timeofdux = "01010001" then
timeofdux <="00000000";
else timeofdux <= timeofdux + 1;
end if;
else timeofdux<= "00000000";
end if;
end if;
end process duxjishi;
end Behavioral;
