VHDL错误：Error (10500): VHDL syntax error at adff.vhd(16) near text "process"; expecting "if"；
Error (10500): VHDL syntax error at adff.vhd(18) near text "rtl"; expecting "if"；
这是在写一个上升沿D触发器，代码如下：
LiBRARY iEEE;
USE ieee.STD_logic_1164.all;
ENTITY adff is
port(clk,d,r,s:in STD_login;
q:out STD_login);
end adff;
architecture rtl of adff is
signal q_temp,qb_temp :std_logic;
begin
process(clk,r,s)
begin
if(r='0' and s='1') then q_temp<='1';
else if (r='1' and s='0') then q_temp<='0';
else if (clk='1') then q_temp<= d;
end if;
end process;
q<=q_temp;
end rtl;
