VHDL分布式算法中的移位累加如何实现？

Question

在用vhdl做滤波器的fpga实现时，尝试采用分布式算法和查表法来优化，因为找到的例子是用的Verilog语言，在写到最后的移位累加时就出现问题了，移位累加无法得到正确的值。想请前辈们帮忙提供一些思路或者经验，我对分布式算法其实也没有弄的太清楚，麻烦各位了
部分代码：
---------------LUT查表---------------------------
LUT1: PROCESS(CLK,TABLEIN1)
BEGIN
IF CLK='1' AND CLK'EVENT THEN
CASE TABLEIN1 IS
WHEN "000" => TABLEOUT1<="0000000000000000";
WHEN "001" => TABLEOUT1<="0000000000000001";
WHEN "010" => TABLEOUT1<="1111111111111010";
WHEN "011" => TABLEOUT1<="1111111111111011";
WHEN "100" => TABLEOUT1<="1111111111110001";
WHEN "101" => TABLEOUT1<="1111111111110010";
WHEN "110" => TABLEOUT1<="1111111111101011";
WHEN "111" => TABLEOUT1<="1111111111111100";
WHEN OTHERS => TABLEOUT1<="ZZZZZZZZZZZZZZZZ";
END CASE;
END IF;
END PROCESS;

LUT2: PROCESS(CLK,TABLEIN2)
BEGIN
IF CLK='1' AND CLK'EVENT THEN
CASE TABLEIN1 IS
WHEN "000" => TABLEOUT2<="0000000000000000";
WHEN "001" => TABLEOUT2<="0000000000011100";
WHEN "010" => TABLEOUT2<="0000000010010000";
WHEN "011" => TABLEOUT2<="0000000010101100";
WHEN "100" => TABLEOUT2<="0000000011010101";
WHEN "101" => TABLEOUT2<="0000000011110001";
WHEN "110" => TABLEOUT2<="0000000101100101";
WHEN "111" => TABLEOUT2<="0000000110000001";
WHEN OTHERS => TABLEOUT2<="ZZZZZZZZZZZZZZZZ";
END CASE;
END IF;
END PROCESS;

--------------查找表累加------------------------------
LUT_ADD: PROCESS(TABLEOUT1,TABLEOUT2)
BEGIN
DATA_ALL_OUT<=(TABLEOUT1(15)&TABLEOUT1)+(TABLEOUT2(15)&TABLEOUT2);
END PROCESS;
--------------移位累加--------------------
ACC_SUB: PROCESS(CLK,DATA_ALL_OUT,ADD_SUB)
VARIABLE ATEMP : STD_LOGIC_VECTOR(17 DOWNTO 0);
BEGIN
IF CLK='1' AND CLK'EVENT THEN

        IF(ADD_SUB='0') THEN
         ATEMP:="000000000000000000";
         ATEMP(17 DOWNTO 0):=ATEMP(17 DOWNTO 0)+(DATA_ALL_OUT(16)&DATA_ALL_OUT);  -- 
         ATEMP:=ATEMP(17)&ATEMP(17 DOWNTO 1);--因系数经量化放大512，故此处可向右移除以215

        ELSE 
         ATEMP(17 DOWNTO 0):=ATEMP(17 DOWNTO 0)-(DATA_ALL_OUT(16)&DATA_ALL_OUT);--因是有符号运算，需将结果用补码表示且每九个周期输出一次
         RESULT<=ATEMP(17 DOWNTO 1)+ATEMP(0);
         ATEMP:="000000000000000000";
         END IF;
       END IF;
     END PROCESS;