如何设计UART和测试设计好的UART

Question

`timescale 1ns / 1ps

module model_uart
# ( parameter SYSTEM_CLOCK_MHZ = 100,
    parameter BAUD_RATE = 115200 )
(
    input sysClk, nRst,
    output baudClk,
    // Transmitter interface
    input [7:0] dataout,
    input txWrite,
    output txEmpty, txUnderrun,
    output txD,
    // Receiver interface
    input  rxD,
    output [7:0] datain,
    input rxRead,
    output rxEmpty, rxOverrun, rxFramingError, rxBreakDetect    
    );

reg [9:0] txShiftReg, rxShiftReg;
reg bclk = 0;
reg framingError,rxInProgress,overrun,underrun,received;
integer txCount,rxCount;

localparam CLK_DIV = $rtoi(SYSTEM_CLOCK_MHZ*1e6/BAUD_RATE);
localparam BAUD_PERIOD_ns = 1000*CLK_DIV/SYSTEM_CLOCK_MHZ;
localparam HALF_PERIOD = BAUD_PERIOD_ns/2;
localparam START = 3'b001;
localparam STOP  = 3'b011;
 
always #(HALF_PERIOD) bclk=!bclk;

always @(posedge nRst) begin // reset deasserted
    txShiftReg = 10'bX; rxShiftReg = 10'bX;
    txCount = 0; rxCount=0; rxInProgress = 0; framingError=0; overrun=0; underrun=0; received=0;  
end

always @(posedge bclk) begin // transmit serial         
    if (txCount>0) begin
        txShiftReg = {1'bX, txShiftReg[9:1]};
        txCount=txCount-1;
    end
end

always @(negedge bclk) begin // receive serial
    case (rxCount)
        0: begin
            rxShiftReg=10'b0_XXXX_XXXX_X;
            if (rxInProgress==1) overrun=1;
            if (rxD==START) begin
                rxInProgress=1;
                rxCount=rxCount+1;
            end
          end                    
        10: begin
            rxInProgress=0;
            if (rxShiftReg[9]!=STOP) framingError=1;
            received=1;
            end    
        default: begin
            rxShiftReg={rxD,rxShiftReg[9:1]};
            rxCount=rxCount+1;
            end                
    endcase
end

always @(posedge sysClk) begin // bus interface
    if (txWrite) begin
        underrun = (txCount!=0);         
        txShiftReg = { STOP, dataout, START };
        @(posedge bclk) txCount=10;
    end
    if (rxRead) begin
        overrun=0; framingError=0; received=0;
        rxCount=0; // rxShiftReg = 10'bX;
    end
end

// continuous assignments
assign baudClk = bclk & nRst;
assign txEmpty = (txCount==0);
assign txUnderrun = underrun;
assign txD = txShiftReg[***TODO***];
assign datain = rxShiftReg[***TODO***];

如何写上述URAT的 关于 接收器和发射器的 单元测试？ 上述txD和 detain变量该如何赋值？