2021-04-25 16:34

# 带占空比显示的pwm信号发生器

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• CSDN专家-黄老师 2021-04-25 18:33
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``````module xuanpin #
(parameter N=25)
(clk,clr,key_in_f,key_in_z,f_out);
input clk,clr,key_in_f,key_in_z;
output reg f_out;
reg clk0,clk1,clk2,clk3,clk4,clk5,clk6,clk7;
wire key;
wire key_z;
reg[8:0] cnter0;
reg[3:0] cnter1,cnter2,cnter3,cnter4,cnter5,cnter6,cnter7,cnter8;
debounce xiaodou_ut
(
.clk(clk),
.rst_n(clr),
.key_n(key_in_f),
.key_pulse(key),
.key_state()
);
debounce xiaodou_uut
(
.clk(clk),
.rst_n(clr),
.key_n(key_in_z),
.key_pulse(key_z),
.key_state()
);
reg [2:0] cnter9,z;
always@(posedge clk or negedge clr)
if (~clr) cnter9<=0;
else if(cnter9==4)cnter9<=0;
else if(key_z) cnter9<=cnter9+1;

always@(posedge clk or negedge clr)
if (~clr)
cnter0<=0;
else if (cnter0==N-1)
begin cnter0<=0;clk0<=1;end
else if(cnter0<=(25*(cnter9+1))) begin clk0<=1;cnter0<=cnter0+1;end
else
begin cnter0<=cnter0+1;clk0<=0;end//100k

always@(posedge clk0 or negedge clr)
if (~clr)
cnter1<=0;
else if(cnter1==9)begin cnter1<=0; clk1<=1;end
else if(cnter1<=(cnter9+1)) begin clk1<=1;cnter1<=cnter1+1;end
else begin cnter1<=cnter1+1;clk1<=0; end//10k

always@(posedge clk1 or negedge clr)
if (~clr)
cnter2<=0;
else if (cnter2==9) begin cnter2<=0;clk2<=1; end
else if(cnter2<=(cnter9+1)) begin clk2<=1;cnter2<=cnter2+1;end
else begin cnter2<=cnter2+1;clk2<=0;end//1000

always@(posedge clk2 or negedge clr)
if (~clr)
cnter3<=0;
else if (cnter3==9) begin cnter3<=0; clk3<=1;end
else if(cnter3<=(cnter9+1)) begin clk3<=1;cnter3<=cnter3+1;end
else begin cnter3<=cnter3+1; clk3<=0;end //100

/*always@(posedge clk2 or negedge clr)
if (~clr) clk3<=0;
else if(cnter3<key_z)clk3<=1;
else clk3<=0;*/

always@(posedge clk3 or negedge clr)
if (~clr) cnter4<=0;
else if(cnter4==9) begin cnter4<=0; clk4<=1;end
else if(cnter4<=(cnter9+1)) begin clk4<=1; cnter4<=cnter4+1;end
else begin cnter4<=cnter4+1;clk4<=0;end //10

/*always@(posedge clk3 or negedge clr)
if (~clr) clk4<=0;
else if(cnter4<key_z)clk4<=1;
else clk4<=0;*/

always@(posedge clk or negedge clr)
if (~clr)
cnter5<=0;
else if(cnter5==9) begin cnter5<=0;clk5<=1; end
else if(cnter5<=(cnter9+1)) begin clk5<=1;cnter5<=cnter5+1;end
else begin cnter5<=cnter5+1;clk5<=0;end//2500k

/*always@(posedge clk or negedge clr)
if (~clr) clk5<=0;
else if(cnter5<key_z)clk5<=1;
else clk5<=0;*/

always@(posedge clk5 or negedge clr)
if (~clr)
cnter6<=0;
else if(cnter6==9) begin cnter6<=0; clk6<=1; end
else if(cnter6<=(cnter9+1))begin clk6<=1;cnter6<=cnter6+1;end
else begin cnter6<=cnter6+1;clk6<=0;end//250k

/*always@(posedge clk5 or negedge clr)
if (~clr) clk6<=0;
else if(cnter6<key_z)clk6<=1;
else clk6<=0;
*/

always@(posedge clk6 or negedge clr)
if (~clr)
cnter7<=0;
else if(cnter7==9) begin cnter7<=0;clk7<=1; end
else if(cnter7<=(cnter9+1)) begin clk7<=1;cnter7<=cnter7+1;end
else begin cnter7<=cnter7+1; clk7<=0;end//25k

/*always@(posedge clk6 or negedge clr)
if (~clr) clk7<=0;
else if(cnter7<key_z)clk7<=1;
else clk7<=0; */

always@(posedge clk or negedge clr)
if (~clr) cnter8<=0;
else if(cnter8==8)cnter8<=0;
else if(key) cnter8<=cnter8+1;

always@(cnter8)
case(cnter8)
0:f_out=clk0;
1:f_out=clk1;
2:f_out=clk2;
3:f_out=clk3;
4:f_out=clk4;
5:f_out=clk5;
6:f_out=clk6;
7:f_out=clk7;
endcase
endmodule

非固定占空比的实现（频率调节，占空比会跟着发生变化）

module Pulse_gen
(
input clk_in,
input rst_n_in,
input key_menu,
input key_up,
input key_down,
output menu_state,
output reg pulse_out
);

//Debounce for key_menu
debounce Debounce_menu(.clk(clk_in),.rst_n(rst_n_in),.key_n(key_menu),.key_state(menu_state));

//Debounce for key_up
debounce Debounce_up(.clk(clk_in),.rst_n(rst_n_in),.key_n(key_up),.key_pulse(up_pulse));

//Debounce for key_down
debounce Debounce_down(.clk(clk_in),.rst_n(rst_n_in),.key_n(key_down),.key_pulse(down_pulse));

reg [3:0] cycle;
reg [3:0] duty;
//Control cycle and duty cycle
always @(posedge clk_in or negedge rst_n_in) begin
if(!rst_n_in) begin
cycle<=4'd8;
duty<=4'd4;
end else begin
if(menu_state) begin//高电平周期调节，低电平占空比调节
if(up_pulse && (cycle<4'd15)) cycle <= cycle + 4'd1;
else if(down_pulse && (cycle>(duty+4'd1))) cycle <= cycle - 4'd1;
else cycle <= cycle;
end else begin
if(up_pulse && (cycle>(duty+4'd1))) duty <= duty + 4'd1;
else if(down_pulse && (duty>4'd0)) duty <= duty - 4'd1;
else duty <= duty;
end
end
end

reg [3:0] cnt;
//counter for cycle
always @(posedge clk_in or negedge rst_n_in) begin
if(!rst_n_in) begin
cnt<=4'd0;
end else begin
if(cnt>=cycle) cnt<=4'd0;
else cnt <= cnt + 4'd1;
end
end

//pulse generate with duty
always @(posedge clk_in or negedge rst_n_in) begin
if(!rst_n_in) begin
pulse_out<=1'b1;
end else begin
if(cnt<=duty) pulse_out<=1'b1;
else pulse_out<=1'b0;
end
end

endmodule
``````
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• 有问必答小助手 2021-04-26 10:46

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• 有问必答小助手 2021-04-26 17:13

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