数字电子技术实验设计

Question

秒表显示时间为四个十进制数，从0.00.0~9.59.9（分.秒.100毫秒）循环计数；包含一个清零信号clr，是秒表返回00.0；包含一个启动信号go，控制开始或是暂停计数；添加一个额外的信号up，用来控制计数方向（加法计数或减法计数）用vivado写的代码， 已完成

Answer 1

module stopwatch(
    input wire clk,
    input wire reset,
    input wire go,
    input wire clr,
    input wire up,
    output reg [3:0] minute,
    output reg [6:0] second,
    output reg [3:0] millisecond
);

reg [3:0] min_reg;
reg [6:0] sec_reg;
reg [3:0] ms_reg;

always @ (posedge clk, posedge reset) begin
    if (reset) begin
        min_reg <= 4'b0000;
        sec_reg <= 7'b0000000;
        ms_reg <= 4'b0000;
    end else begin
        if (go) begin
            if (up) begin
                if (ms_reg == 4'b1001) begin
                    ms_reg <= 4'b0000;
                    if (sec_reg == 7'b5959999) begin
                        sec_reg <= 7'b0000000;
                        min_reg <= min_reg + 4'b0001;
                    end else begin
                        sec_reg <= sec_reg + 7'b0000001;
                    end
                end else begin
                    ms_reg <= ms_reg + 4'b0001;
                end
            end else begin
                if (ms_reg == 4'b0000) begin
                    ms_reg <= 4'b1001;
                    if (sec_reg == 7'b0000000) begin
                        sec_reg <= 7'b5959999;
                        min_reg <= min_reg - 4'b0001;
                    end else begin
                        sec_reg <= sec_reg - 7'b0000001;
                    end
                end else begin
                    ms_reg <= ms_reg - 4'b0001;
                end
            end
        end else begin
            // do nothing
        end
        
        if (clr) begin
            min_reg <= 4'b0000;
            sec_reg <= 7'b0000000;
            ms_reg <= 4'b0000;
        end
    end
end

assign minute = min_reg;
assign second = sec_reg[6:0];
assign millisecond = ms_reg;

endmodule