verilog使用串口调试助手发送数据处理后接受,出现如下问题? 10C

要求:经串口调试助手发送6个数后对这6个数进行排序,再在调试助手接收端显示排完序的数据
代码如下:

module cal(
    input clk,
    input rxf,
    input txe,
    input key,
    input[7:0] datain,
    output reg[7:0] dataout,
    output over,
    output reg wr,
    output reg rd,
    output reg SI
    );
    reg [24:0]sample;
    reg sig_r0;
    reg sig_r1;
    wire rst;
    reg clear_key;
    reg last_key;
    reg [7:0] memo[5:0];
    integer i,j,m,n;
    reg [4:0]state;
    reg [7:0]buffer;
    reg div_clk;
    reg div_clk2;
    initial begin
        state <= 0;
        wr <= 0;
        rd <= 1;
        SI <= 1;
    end
    task exchange(
        inout[7:0] x,y
        );  
        reg[7:0] temp;
        begin
        if(x<y)
      begin
        temp=x;
        x=y;
        y=temp;
      end
        end
    endtask
    always @(posedge clk)
    begin   
        div_clk <= ~div_clk;
    end
    always @(posedge div_clk)
    begin   
        div_clk2 <= ~div_clk2;
    end
        always @(posedge div_clk2)
    begin
        if(sample==120000)
        begin
            last_key <= key;
            sample <= 0;
            if(last_key == key)
            begin
                clear_key <= key;
            end
        end
        else
            sample <= sample+1;
    end
    always @ (posedge div_clk2)
    begin
    sig_r0 <= clear_key;
    sig_r1 <= sig_r0;
    end 
    assign rst = sig_r1 & (~sig_r0);
    always @(posedge div_clk2)
        if(rst)
        begin
            i=0;
            j=0;
            m=0;
            n=0;
        end
        else
        begin
                    case(state)
            5'd0:   begin
                        if(rxf == 0)begin
                            rd <= 0;
                            state <= 1;
                            end
                    end
            5'd1:   begin
                        if(m<6)
                            begin
                                memo[m] <= datain ;
                                m=m+1;
                                state <= 1;
                        end 
                        else begin
                                rd <= 1;
                                state <= 2;
                    end
                    end
            5'd2:   begin
                        if(txe == 0)begin
                            if(i==6) 
                            begin
                                    i=6;                
                                    dataout <= memo[n];
                                    n=n+1;
                                    wr <= 1;
                                    state <= 5'd3;                          
                            end
                        end
                        if(i<6)
                            for(i=0;i<6;i=i+1)       
                            begin
                                for(j=0;j<5-i;j=j+1) 
                                exchange(memo[j+1],memo[j]); 
                            end
                    end
            5'd3:   begin
                            if(n<6)begin
                                wr <= 0;
                                state <= 5'd2;
                            end else begin
                                wr <= 0;
                                state <= 5'd4;
                            end                 
                    end
            5'd4:   begin
                        SI <= 0;
                        state <= 5'd5;
                    end 
            5'd5:   begin
                        SI <= 1;
                        state <= 5'd0;
                    end                     
            default:state <= 0;
        endcase
        end
    assign data = (state==5'd3)?dataout:8'bzzzz_zzzz;
endmodule 

烧录运行结果如下:
图片说明
本人初学者,求大神指点错误

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