这段程序实现的是计算输入位中为1的个数并赋值给输出
module top_module(
input [2:0] in,
output [1:0] out );
assign out=2'b0;
genvar i;
generate
for(i=0;i<3;i=i+1)begin:x
if(in[i]==1)begin
out=out+1;
end
end
endgenerate
endmodule
然后报错在
Error (10170): Verilog HDL syntax error at top_module.v(9) near text: "="; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /home/h/work/hdlbits.3327919/top_module.v Line: 9
Error (10112): Ignored design unit "top_module" at top_module.v(1) due to previous errors File: /home/h/work/hdlbits.3327919/top_module.v Line: 1
麻烦解答一下 谢谢!
verilog程序报错
- 写回答
- 好问题 0 提建议
- 追加酬金
- 关注问题
- 邀请回答
-
1条回答 默认 最新
- 老皮芽子 2022-01-18 09:55关注
module top_module ( input [2:0] in, output [1:0] out ); reg out_r = 0; assign out = out_r; genvar i; generate always@(in) begin for(i=0;i<3;i=i+1) begin:x out_r = out_r + in[i]; end end endgenerate endmodule
解决 无用评论 打赏 举报
悬赏问题
- ¥20 蓝牙耳机怎么查看日志
- ¥15 Fluent齿轮搅油
- ¥15 八爪鱼爬数据为什么自己停了
- ¥15 交替优化波束形成和ris反射角使保密速率最大化
- ¥15 树莓派与pix飞控通信
- ¥15 自动转发微信群信息到另外一个微信群
- ¥15 outlook无法配置成功
- ¥30 这是哪个作者做的宝宝起名网站
- ¥60 版本过低apk如何修改可以兼容新的安卓系统
- ¥25 由IPR导致的DRIVER_POWER_STATE_FAILURE蓝屏