3.1.3.5 Signed addition overflow(Exams/ece241 2014 q1c)
Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred.
关于溢出我想用同或异或表示,为啥一直显示出错,劳烦大家帮忙解惑
module top_module (
input [7:0] a,
input [7:0] b,
output [7:0] s,
output overflow
); //
assign s=a+b[7:0];
always @(b[7],a[7])
if (b[7]~^a[7])
overflow = 1;
else overflow = 0;
主要是overflow的波形匹配不上,下面是给的结果
刚开始学习,请大家不吝赐教