tessent检测stuck-at fault时报错？

Question

使用tessent监测stuck-at-fault时，输入一个测试向量时可以正常运行。但是输入两个测试向量时，报错如下：这要怎么修改吼？？

//  command: set_context patterns -scan
//  command: read_verilog full_adder.v
//  command: set_current_design full_adder
//  Warning: 1 case: Undriven net in netlist module
//  Note: Issue set_current_design with the -show_elaboration_warnings option to see more details about previous warnings
//  command: set_system_mode analysis
//  Warning: Rule FN1 violation occurs 1 times
//  Flattening process completed,  netlist_primitive=5  sim_gates=12  PIs=3  POs=2  CPU time=0.00 sec.
//  ---------------------------------------------------------------------------
//  Begin circuit learning analyses.
//  --------------------------------
//  Learning completed, CPU time=0.00 sec.
//  ---------------------------------------------------------------------------
//  Begin scan chain identification process, memory elements = 0.
//  ---------------------------------------------------------------------------
//  Circuit has no memory elements.
//  command: set_pattern_source external full_adder.ascii
//  Error: Line 14: syntax error.
//  External test pattern set has been deleted due to error.
// 'DOFile full_adder.do' aborted at line 7

```c++
"full_adder.v"：文件如下：
module full_adder(a,b,ci,si,cout);
        input a,b,ci;
        output si,cout;
        wire n,o,p;
        xor XOR1(si,a,b,c);
        and AND1(n,a,b);
        and AND2(o,a,c);
        and AND3(p,b,c);
        or OR1(cout,n,o,p);
endmodule

```c++
"full_adder.run"文件如下：
/eda-tools/Mentor/Tessent/tessent_tree_2015.4/bin/tessent -shell -dofile full_adder.do -logfile full_adder.log -replace

"full_adder.do"文件如下：
set_context patterns -scan
read_verilog full_adder.v
set_current_design full_adder
set_system_mode analysis
//run fault simulation
set_pattern_source external full_adder.ascii
add_faults -All
simulate_patterns
report_statistics
report_faults -class DS
reset state
exit -d

"full_adder.ascii"文件如下：
ASCII_PATTERN_FILE_VERSION = 2;
SETUP =
    declare input bus "PI" = "/a","/b","/ci";
    declare output bus "PO" = "/si","/cout";
end;
SCAN_TEST =
    pattern = 0;
    force "PI" "110" 0;
    measure "PO" "10" 1;
end;
SCAN_TEST =
    pattern = 1;
    force "PI" "001" 0;
    measure "PO" "01" 1;
end;