quartus仿真正确，但是modelsim里面波形全部都是红色线，变量也都显示不定态x或者stx猜测是test文件有问题，照着教程赋初值以后总报错，大概率是自己的veilog语言太差，请各位看看问题，以下是测试文件
```bash
// Copyright (C) 2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors. Please
// refer to the applicable agreement for further details.
// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to
// suit user's needs .Comments are provided in each section to help the user
// fill out necessary details.
// *****************************************************************************
// Generated on "12/20/2023 21:12:41"
// Verilog Test Bench template for design : ZJiaotongD
//
// Simulation tool : ModelSim-Altera (Verilog)
//
`timescale 1 ps/ 1 ps
module ZJiaotongD_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg key0;
reg rst_n;
// wires
wire hex0;
wire hex1;
wire hex2;
wire hex3;
wire hex4;
wire hex5;
wire hex6;
wire hex7;
wire hex8;
wire hex9;
wire hex10;
wire hex11;
wire hex12;
wire hex13;
wire hex14;
wire hex15;
wire hex16;
wire hex17;
wire hex18;
wire hex19;
wire hex20;
wire hex21;
wire hex22;
wire hex23;
wire hex24;
wire hex25;
wire hex26;
wire hex27;
wire led0;
wire led1;
wire led2;
wire led3;
wire led4;
wire led5;
// assign statements (if any)
ZJiaotongD i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.hex0(hex0),
.hex1(hex1),
.hex2(hex2),
.hex3(hex3),
.hex4(hex4),
.hex5(hex5),
.hex6(hex6),
.hex7(hex7),
.hex8(hex8),
.hex9(hex9),
.hex10(hex10),
.hex11(hex11),
.hex12(hex12),
.hex13(hex13),
.hex14(hex14),
.hex15(hex15),
.hex16(hex16),
.hex17(hex17),
.hex18(hex18),
.hex19(hex19),
.hex20(hex20),
.hex21(hex21),
.hex22(hex22),
.hex23(hex23),
.hex24(hex24),
.hex25(hex25),
.hex26(hex26),
.hex27(hex27),
.key0(key0),
.led0(led0),
.led1(led1),
.led2(led2),
.led3(led3),
.led4(led4),
.led5(led5),
.rst_n(rst_n)
);
initial
begin
// code that executes only once
// insert code here --> begin
// --> end
$display("Running testbench");
end
always
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
@eachvec;
// --> end
end
endmodule
