在运行代码时,显示器上无法显示图像,是线的问题?电脑的问题?还的代码问题?
vivado代码:
module clk_unit( //4分频
input clock,
input rst,
output vga_clk
);
reg vga_clk;
reg clk_tmp;
always @(posedge clk_tmp or posedge rst) begin
if (rst)
vga_clk <= 0;
else
vga_clk <= ~vga_clk;
end
always @(posedge clock or posedge rst) begin
if (rst)
clk_tmp <= 0;
else
clk_tmp <= ~clk_tmp;
end
endmodule
module lab_VGA(
input clock, //系统时钟100MHZ
input rst, //时钟复位端
input [1:0] switch, //显示模式选择
output [2:0] disp_RGB, // VGA数据输出
output hsync, // VGA行同步信号
output vsync // VGA场同步信号
);
wire clock, rst;
wire hsync,vsync;
reg[9:0] hcount; // 行扫描计数器
reg[9:0] vcount; // 场扫描计数器
reg [2:0] data; //数据端
reg [2:0] h_data; //横彩条
reg [2:0] v_data; //竖彩条
wire vga_clk; //25M的VGA时钟
wire hcount_ov; //行扫描结束标志位
wire vcount_ov; //帧扫描结束标志位
wire data_act; //激活标志,当这个信号为1时RGB的数据可以显示在屏幕上
//分辨率为640*480时行、场时序各个参数定义
parameter hsync_end = 10'd95, //a行同步信号(低电平)结束
hdata_begin = 10'd143, //b显示后延结束,c行显示开始(144)
hdata_end = 10'd783, //行显示结束
hpixel_end = 10'd799, //行显示前延结束
vsync_end = 10'd1,//o结束
vdata_begin = 10'd34,//p结束
vdata_end = 10'd514,//q结束
vline_end =10'd524;//f结束
//生成VGA时钟
clk_unit myclk(
.clock(clock),
.rst(rst),
.vga_clk(vga_clk)
);
//VGA驱动程序
//行扫描
assign hcount_ov = (hcount == hpixel_end);
//行计数器=799,扫描一行结束,给出标志位 1
always@(posedge vga_clk) //最好加上rst信号!
begin
if(hcount_ov) //若行扫描标志位为1,换行
hcount<=10'd0; //行扫描计数器置0
else
hcount<= hcount +10'd1; //行扫描计数器+1
end
//场扫描
assign vcount_ov = (vcount == vline_end);
//场计数器=524,一帧显示结束,给出标志位 1
always@(posedge vga_clk)
begin
if(hcount_ov) //行扫描标志位有效
begin
if(vcount_ov) //帧扫描标志位有效,场扫描计数器置零,重新计数
vcount<=10'd0;
else
vcount<= vcount +10'd1; //场扫描计数器加1
end
end
//数据、同步信号输出
assign data_act = ((hcount>hdata_begin) && (hcount<=hdata_end))&&
((vcount>vdata_begin)&& (vcount<=vdata_end)); //显示阶段
assign hsync = (hcount > hsync_end);//行计数器大于95,行同步信号置1
assign vsync = (vcount > vsync_end); //场计数器大于1,场同步信号置1
assign disp_RGB = (data_act) ? data : 3'b000;
//显示阶段,输出数据,否则输出0(不显示)
always@(posedge vga_clk)
begin
case(switch[1:0])
2'd0: data<=h_data; //选择横彩条
2'd1: data<=v_data; //选择竖彩条
2'd2: data<=(v_data ^ h_data); //产生棋格 异或 不同为1
2'd3: data<=(v_data ~^ h_data); //产生棋格 同或 相同为1
endcase
end
always@(posedge vga_clk) //产生竖彩条
begin
if(hcount <=223) //96+48-1+640/8=223
v_data<=3'h7;
else if(hcount <=303) //223+80=303
v_data<=3'h6;
else if(hcount <=383) //303+80=383
v_data<=3'h5;
else if(hcount <=463) //383+80=463
v_data<=3'h4;
else if(hcount <=543) //463+80=543
v_data<=3'h3;
else if(hcount <=623) //543+80=623
v_data<=3'h2;
else if(hcount <=703) //623+80=703
v_data<=3'h1;
else
v_data<=3'h0;
end
always@(posedge vga_clk) //产生横彩条
begin
if(vcount <=94) //2+33-1+480/8=94
h_data<=3'h7;
else if(vcount <=154)
h_data<=3'h6;
else if(vcount <=214)
h_data<=3'h5;
else if(vcount <=274)
h_data<=3'h4;
else if(vcount <=334)
h_data<=3'h3;
else if(vcount <=394)
h_data<=3'h2;
else if(vcount <=454)
h_data<=3'h1;
else
h_data<=3'h0;
end
endmodule
约束条件:
set_property IOSTANDARD LVCMOS33 [get_ports {disp_RGB[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {disp_RGB[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {disp_RGB[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switch[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switch[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports clock]
set_property IOSTANDARD LVCMOS33 [get_ports hsync]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports vsync]
set_property PACKAGE_PIN A4 [get_ports {disp_RGB[0]}]
set_property PACKAGE_PIN A6 [get_ports {disp_RGB[1]}]
set_property PACKAGE_PIN D8 [get_ports {disp_RGB[2]}]
set_property PACKAGE_PIN J15 [get_ports {switch[0]}]
set_property PACKAGE_PIN L16 [get_ports {switch[1]}]
set_property PACKAGE_PIN E3 [get_ports clock]
set_property PACKAGE_PIN B11 [get_ports hsync]
set_property PACKAGE_PIN B12 [get_ports vsync]
set_property PACKAGE_PIN N17 [get_ports rst]
代码是ls发的,应该是没什么问题
线用的是vga转hdmi线
最后要呈现出下面的形式:




但我最后显示器却不会显示。