我想用verilog HDL写一个电子时钟（只显示分秒），要附加一个秒表功能但是always不能加入两个posedge，应该怎么改进。

Question

我刚刚学verilog 这是我的代码 现在只是实现现实分秒 怎么改才能加入一个秒表

 module clock_1(clk,Clear,s1,s2,m1,m2,EN1,EN2,EN3);

 input clk,Clear,EN1,EN2,EN3;

 output reg [3:0] s1,s2,m1,m2;

 reg [25:0]count;

 reg carry,second_01s;


initial count=26'b0;

// 每秒产生一个脉冲

  always@(posedge clk)

  begin

   begin 
   if (count==27000000)
   count<=26'b0;
   else
   count<=count+1;
   end

   begin
   if(count==27000000)
   second_01s <=1;
   else
   second_01s <=0;
   end


 end 

//秒

 always@(posedge second_01s  or negedge Clear  )

 begin

          if (!Clear)
          begin
          s1<=0;
          s2<=0;
          carry=0;
      end

     //1s
       else if(EN2)
  begin
       carry=0;
       s1[3:0]<=s1[3:0]+1;
       if(s1[3:0]==9)
     begin
      s1[3:0] <= 0;
      s2[3:0] <= s2[3:0]+1; 
        if (s2[3:0]==5)
          begin
          s2[3:0]<=0;
          carry<=1;
          end
        end
  end            
end 

//分

   always@(posedge carry or negedge Clear)

begin
   if (!Clear)
     begin
     m1<=0;
     m2<=0;
     end

     else if (EN2)
     begin
     m1[3:0]<=m1[3:0]+1;
        if(m1[3:0]==9)
      begin
       m1[3:0] <= 0;
       m2[3:0] <= m2[3:0]+1;    
             if (m2[3:0]==5)
              begin
              m2[3:0]<=0;

              end
         end
     end             
en
endmodule

Answer 1

https://blog.csdn.net/Glasier/article/details/86660287