library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt60 is
port(clk,clr,rst:in std_logic;
sec1:in std_logic_vector(3 downto 0);
sec0:in std_logic_vector(3 downto 0);
sec11:out std_logic_vector(3 downto 0);
sec00:out std_logic_vector(3 downto 0);
co:out std_logic);
end cnt60;
architecture behav of cnt60 is
signal cnt0:std_logic_vector(3 downto 0);
signal cnt1:std_logic_vector(2 downto 0);
signal clk1:std_logic;
begin
a:process(clk,clr,rst)
begin
if rst='1'then cnt0<="0000";
elsif(clk'event and clk='1')and clr='1'then
if cnt0="1001"then
cnt0<="0000";
clk1<='1';
else
cnt0<=cnt0+1;
clk1<='0';
end if;
end if;
end process a;
b:process(rst,clr,clk1)
begin
if rst='1'then cnt1<="000";
elsif(clk1'event and clk1='1')and clr='1'then
if cnt1="101"then
cnt1<="000";
else
cnt1<=cnt1+1;
end if;
end if;
end process b;
c:process(clk,clk1)
begin
if clk'event and clk='1'then
if cnt1="101" and cnt0="1001"then
co<='1';
else
co<='0';
end if;
end if;
end process c;
co(4 downto 0)<=cnt0;
co(7 downto 4)<=cnt1;
end behav;
求各位大神帮忙看下这代码错在哪里，小白求
