library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity dianzhen is
port(
clk,reset:in std_logic;
hang:out std_logic_vector(7 downto 0);
lie:out std_logic_vector(7 downto 0));
end dianzhen;
architecture jg of dianzhen is Signal
chushi:std_logic_vector(23 downto 0):="000000000000000000000000";
signal gaowei:std_logic_vector(1 downto 0);
signal diwei:std_logic_vector(2 downto 0);
begin
process(clk,reset,gaowei,diwei,chushi)
begin
if(reset='1')then chushi<="000000000000000000000000";
else if(reset='0')then
if(clk'event and clk='1')then
chushi<=chushi+1;
end if;
end if;
gaowei(1 downto 0)<=chushi(21 downto 20);
diwei(2 downto 0)<=chushi(2 downto 0);
case diwei is
when"000"=>hang<="10000000";
when"001"=>hang<="01000000";
when"010"=>hang<="00100000";
when"011"=>hang<="00010000";
when"100"=>hang<="00001000";
when"101"=>hang<="00000100";
when"110"=>hang<="00000010";
when"111"=>hang<="00000001";
end case;
if gaowei="00"then
case diwei is
when"000"=>lie<="00000011";
when"001"=>lie<="00000011";
when"010"=>lie<="00000011";
when"011"=>lie<="11111111";
when"100"=>lie<="11111111";
when"101"=>lie<="00000011";
when"110"=>lie<="00000011";
when"111"=>lie<="00000011";
end case;
else if gaowei="01"then
case diwei is
when"000"=>lie<="11111111";
when"001"=>lie<="11111111";
when"010"=>lie<="00011000";
when"011"=>lie<="00011000";
when"100"=>lie<="00111100";
when"101"=>lie<="01100110";
when"110"=>lie<="11000011";
when"111"=>lie<="10000001";
end case;
else if gaowei="10"then
case diwei is
when"000"=>lie<="00100000";
when"001"=>lie<="01100000";
when"010"=>lie<="11000000";
when"011"=>lie<="10000000";
when"100"=>lie<="11000000";
when"101"=>lie<="01100000";
when"110"=>lie<="00111111";
when"111"=>lie<="00011111";
end case;
end if;
end process;
end;
这个error咋解决？一直搞不懂，quartus说 Error (10500): VHDL syntax error at dianzhen.vhd(70) near text ";"; expecting "if"
求解，谢谢。
