用verilog语言描述图中电路

Question

Answer 1

module test (in, clk, rst_n, out);
  input in;
  input clk;
  input rst_n;
  output out;
  
  reg A;
  reg B;
  wire B_reg;

  always @(posedge clk or negedge rst_n) 
  begin
    if(!rst_n)
      begin
          A <= 1'b0;
          B <= 1'b0;
      end
    else
      begin
          A <= B_reg;
          B <= in;
      end
  end
  assign B_reg = B;
  assign out = (~A) & B;
    
endmodule

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