am调制有符号的会了，如何在此基础上用无符号乘法器来设计实现am调制呢

Question

rom表数据产生信号范围0-255，再使用无符号乘法器（自己设计的，不知道有没有错）将两信号相乘得不到正确的调制波形，只出来一半，该怎么做修改呢

module dds(
input wire sclk,
input wire rst,
output wire [15:0] wave
);
parameter M0 = 32'd17179869;//200kHz
parameter M1 = 32'd257698038;//20MHz
reg [31:0] sum0,sum1;
wire [7:0] addr0,addr1;
wire [7:0] wave_200k;
wire [7:0] wave_20M;
always@(posedge sclk or negedge rst)
if(rst == 1'b0)
sum0 <= 'd0;
else
sum0 <= sum0 + M0;
always@(posedge sclk or negedge rst)
if(rst == 1'b0)
sum1 <= 'd0;
else
sum1 <= sum1 + M1;
assign addr0 = sum0[31:24];
assign addr1 = sum1[31:24];
rom_256x8_200k rom_256x8_200k_inst (
.address ( addr0 ),
.clock ( sclk ),
.q ( wave_200k )
);
rom_256x8_20M rom_256x8_20M_inst (
.address ( addr1 ),
.clock ( sclk ),
.q ( wave_20M )
);
mult mult_inst (
.data_a ( wave_200k ),
.data_b ( wave_20M ),
.result ( wave )
);
endmodule

Answer 1

//wave 有符号数，仿真按有符号数来
module dds(
    input wire            sclk,
    input wire            rst,
    output wire [15:0]    wave
);

    parameter M0 = 32'd17179869;//200kHz
    parameter M1 = 32'd257698038;//20MHz

    reg [31:0] sum0,sum1;
    wire [7:0] addr0,addr1;
    wire [7:0] wave_200k;
    wire [7:0] wave_20M;
    wire [15:0] wave_x1;
    wire signed [16:0] wave_x2;

    always@(posedge sclk or negedge rst)
    if(rst == 1'b0)
        sum0 <= 'd0;
    else
        sum0 <= sum0 + M0;

    always@(posedge sclk or negedge rst)
    if(rst == 1'b0)
        sum1 <= 'd0;
    else
        sum1 <= sum1 + M1;

    assign    addr0    = sum0[31:24];
    assign    addr1    = sum1[31:24];
    assign    wave_x2 = wave_x1 + 16384 - (wave_200k << 7) - (wave_20M << 7);
    assign    wave    = wave_x2;

rom_256x8_200k rom_256x8_200k_inst (
    .address ( addr0 ),
    .clock ( sclk ),
    .q ( wave_200k )
);
rom_256x8_20M rom_256x8_20M_inst (
    .address ( addr1 ),
    .clock ( sclk ),
    .q ( wave_20M )
);
mult mult_inst (
    .data_a ( wave_200k ),
    .data_b ( wave_20M ),
    .result ( wave_x1 )
);
endmodule