请问这该怎么解决，编译不了verilog

Question

问题遇到的现象和发生背景

Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Error (12007): Top-level design entity "test" is undefined

Error: Quartus Prime Analysis & Synthesis was unsuccessful. 1 error, 1 warning
Error: Peak virtual memory: 4707 megabytes
Error: Processing ended: Tue Mar 15 21:09:00 2022
Error: Elapsed time: 00:00:15
Error: Total CPU time (on all processors): 00:00:31
Error (293001): Quartus Prime Full Compilation was unsuccessful. 3 errors, 1 warning

问题相关代码，请勿粘贴截图

`timescale 1 ns / 1 ps

module sum ( A ,Co ,B ,S ,Ci );

input A ;
wire A ;
input B ;
wire B ;
input Ci ;
wire Ci ;

output Co ;
reg Co ;
output S ;
reg S ;

always @ ( A or B or Ci)
begin
if ( A== 0 && B == 0 && Ci == 0 )
begin
S <= 0;
Co <= 0;
end
else if ( A== 1 && B == 0 && Ci == 0 )
begin
S <= 1;
Co <= 0;
end
else if ( A== 0 && B == 1 && Ci == 0 )
begin
S <= 1;
Co <= 0;
end
else if ( A==1 && B == 1 && Ci == 0 )
begin
S <= 0;
Co <= 1;
end
else if ( A== 0 && B == 0 && Ci == 1 )
begin
S <= 1;
Co <= 0;
end
else if ( A== 1 && B == 0 && Ci == 1 )
begin
S <= 0;
Co <= 1;
end
else if ( A== 0 && B == 1 && Ci == 1 )
begin
S <= 0;
Co <= 1;
end
else
begin
S <= 1;
Co <= 1;
end
end

endmodule

运行结果及报错内容

我的解答思路和尝试过的方法

我想要达到的结果

Answer 1

多半是因为工程名和顶层名不一致。