想练一下封装功能块的时候遇到了一个报错
`timescale 1ns/1ps
module minganxinhaoliebiao();
wire clk,rst;//这里的值是在调用模块中产生的,所以是wire
reg test1;
reg a,b,c,d;
//调用层例化
sys_ctrl_task sys_ctrl(
.clk (clk),
.rst (rst)
);
initial begin
sys_ctrl.sys_rst(200);
#1000;
write;
end
endmodule
//************************************
//调用层
//***********************************
module sys_ctrl_task(clk,rst);
output reg clk;
output reg rst;
parameter PERIOD = 20; //时钟周期/ns
parameter RST_ING = 1'b0; //有效复位值
initial begin
clk = 0;
forever
#(PERIOD/2) clk = ~clk;
end
//----------------------------------------
//任务封装
//-----------------------------------------
task sys_rst;
input [31:0] rst_time;
begin
rst = RST_ING;
#rst_time;
rst = ~RST_ING;
end
endtask
endmodule
Error (10207): Verilog HDL error at minganxinhaoliebiao.v(16): can't resolve reference to object "sys_rst"
Error (12153): Can't elaborate top-level user hierarchy
但是我的sys_rst是定义的了啊,为什么还会报这种错