vivado，综合后遇见错误

Question

综合时出现[Synth 8-349] instance 'ledio' of module 'LED_switch' passed 10 connections, but takes just 9 ["D:/vivado/project_IO/project_IO.srcs/sources_1/new/top.v":69]

module LED_switch(
input iow,
input clk,
input a,
input [31:0] DataIn,
output [31:0] Dataout,
input [7:0] switch0,
input [7:0] switch1,
output [7:0] led0,
output [7:0] led1
);
assign Dataout=(a==1'b0)?{24'h0,switch0}:{24'h0,switch1};
reg[7:0] regled[1:0];
assign led0=regled[0];
assign led1=regled[1];
always @(negedge clk)
begin
if(iow)
if(a==0)
regled[0]<=DataIn[7:0];
else
regled[1]<=DataIn[7:0];
end
endmodule
寄存器模块：
module regFile(
input clk,
input reset,
input [4:0] RsAddr,
input [4:0] RtAddr,
input [4:0] WriteAddr,
input [31:0] WriteData,
input regwr,
output [31:0] RsData,
output [31:0] RtData
);

reg[31:0] regs[0:31];//
assign RsData=(RsAddr==5'b0)?32'h0:regs[RsAddr];
assign RtData=(RtAddr==5'b0)?32'h0:regs[RtAddr];
integer i;
always@(negedge clk or posedge reset)
 if(reset)
    for(i=1;i<32;i=i+1)
        regs[i]<=0;
 else if (regwr)
        regs[WriteAddr]<=WriteData;

endmodule
顶层模块：
module top(
input clk,
input reset_ext,
input [15:0] switch,
output [15:0] led
);
reg[31:0] PC;
wire J,B,RegDst,RegWr,ALUSrc,zero,Mem2Reg,MemWr,Bzero;//控制信号
wire [1:0] ALUop;
wire [3:0] ALUctr;
wire [31:0] Instr,RtData,RsData,in2,res,Dataout,WriteData;
wire [31:0] NewPC,JMPC,BPC,NotJMMPC,BranPC,TempPC,Imm32,ImmL2;
wire [4:0]WriteAddr;
wire iow,memw;
wire [31:0] IODataout,memDataout;
wire reset;

assign Imm32={{16{Instr[15]}},Instr[15:0]};
assign WriteAddr=RegDst?Instr[15:11]:Instr[20:16];
assign in2=ALUSrc?Instr[15:0]:RtData;
assign WriteData=Mem2Reg?Dataout:res;
assign NotJMMPC=Bzero?BranPC:NewPC;
assign TempPC=J?JMPC:BranPC;
assign Bzero=B&zero;
assign NewPC=PC+4;
assign ImmL2=ALUSrc<<2;
assign JMPC={NewPC[31:28],Instr[25:0],2'b00};
assign BranPC=NewPC+ImmL2;
assign memw=~res[7]&MemWr;
assign iow=res[7]&MemWr;
assign Dataout=res[7]?IODataout:memDataout;
assign reset=~reset_ext;
    
always @(posedge clk)
     if(!reset)
        PC=TempPC;
     else
        PC=32'b0;
mainctr mainctr1(Instr[31:26],ALUop,RegDst,RegWr,ALUSrc,MemWr,B,J,Mem2Reg);
ALU alu(RsData,zero,res,ALUctr,in2);
regFile regf1(clk,reset,Instr[25:21],Instr[20:16],WriteAddr,WriteData,RegWr,RsData,RtData);
DataRAM dram(.a(res[7:2]),.d(RtData),.clk(!clk),.spo(memDataout),.we(memw));
InstrROM irom(.a(PC[8:2]),.spo(Instr));
LED_switch ledio(iow,clk,,res[2],RtData,IODataout,switch[7:0],switch[15:8],led[7:0],led[15:8]);

endmodule

运行结果：
[Synth 8-349] instance 'ledio' of module 'LED_switch' passed 10 connections, but takes just 9 ["D:/vivado/project_IO/project_IO.srcs/sources_1/new/top.v":69]

Answer 1

这行代码中 clk 后面连着 2 个逗号，去掉一个就行
LED_switch ledio(iow,clk,,res[2],RtData,IODataout,switch[7:0],switch[15:8],led[7:0],led[15:8]);