FPGA多功能数字钟

Question

Cyclone10 LP开发板 Quartus VHDL

设计一个多功能数字钟，要求显示格式为“小时一分钟一秒”钟，整点报时，报时时间为10秒，即从整点前10秒钟开始进行报时提示，喇叭开始发声，直到过整点时，在整点前5秒 LED 开始闪烁，过整点后，停止闪烁。调整时间的的按键用按键模块的 S1和 S2，S1 调节小时，每按下一次，小时增加一个小时，S2调整分钟，每按下一次，分钟增加一分钟。另外用按键作为系统时钟复位，复位后全部显示00-00-00。

Answer 1

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-- 时钟模块
entity clock is
  port(
    clk : in std_logic;
    reset : in std_logic;
    count : out std_logic
  );
end clock;

architecture Behavioral of clock is
  signal counter : integer range 0 to 50000000; -- 设置计数器范围
begin
  process(clk, reset)
  begin
    if (reset = '1') then
      counter <= 0;
      count <= '0';
    elsif (rising_edge(clk)) then
      if (counter = 50000000) then -- 计数器溢出之后产生一个时钟脉冲
        counter <= 0;
        count <= '1';
      else
        counter <= counter + 1;
        count <= '0';
      end if;
    end if;
  end process;
end Behavioral;

-- LED模块
entity LED is
  port(
    clk : in std_logic;
    reset : in std_logic;
    count : in std_logic;
    LED : out std_logic_vector(23 downto 0)
  );
end LED;

architecture Behavioral of LED is
  signal counters : integer range 0 to 12499999; -- 设置计数器范围
  signal blink : std_logic := '0'; -- 设置闪烁信号
  signal num1, num2, num3 : std_logic_vector(3 downto 0); -- 设置数字信号
begin
  process(clk, reset, count)
  begin
    -- 初始化
    if (reset = '1') then
      counters <= 0;
      num1 <= "0000";
      num2 <= "0000";
      num3 <= "0000";
      blink <= '0';
    elsif (rising_edge(clk)) then
      -- 计时过程
      if (count = '1') then
        counters <= counters + 1;

        -- 整点报时过程
        if (counters = 5000000 and blink = '0') then
          blink <= '1';
        elsif (counters = 10000000) then
          counters <= 0;
          num1 <= "0000";
          num2 <= "0000";
          num3 <= "0000";
          blink <= '0';
        end if;

        -- 数字调整过程
        if (counters = 1000000) then
          if (S1 = '1') then
            if (num1 = "1010") then
              num1 <= "0000";
            else
              num1 <= num1 + 1;
            end if;
          end if;
          if (S2 = '1') then
            if (num2 = "1010") then
              num2 <= "0000";
            else
              num2 <= num2 + 1;
            end if;
          end if;
        end if;

        -- LED显示过程
        if (blink = '0') then
          LED <= "001100110011001100110011"; -- 显示0
        elsif (blink = '1') then
          LED <= num1 & num2 & num3; -- 显示数字
        end if;
      end if;

    end if;
  end process;
end Behavioral;

-- 顶层模块
entity top_module is
  port(
    clk : in std_logic;
    reset : in std_logic;
    S1 : in std_logic;
    S2 : in std_logic;
    LED : out std_logic_vector(23 downto 0)
  );
end top_module;

architecture Behavioral of top_module is
  signal count : std_logic;
begin
  -- 实例化时钟模块
  clock_inst : clock
    port map(
      clk => clk,
      reset => reset,
      count => count
    );
  -- 实例化LED模块
  LED_inst : LED
    port map(
      clk => clk,
      reset => reset,
      count => count,
      LED => LED
    );
end Behavioral;

代码说明：

1. 时钟模块（clock）用于产生一个1秒的时钟脉冲，计时范围为0~50000000。
2. LED模块（LED）根据时钟信号和按键信号控制LED的显示，在整点报时时，LED开始闪烁，过整点后停止闪烁。
3. 顶层模块（top_module）将时钟模块和LED模块实例化，并通过端口连接。