Verilog设计秒表vivado

Question

用Verilog语言(vivado2018.3版本可运行)写一个电子秒表的代码，具有启动，暂停，归位，记录七次数据的功能。数码管显示时、分、秒、毫秒。(可上板Artix－7)

Answer 1

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当然，下面是一个基于Verilog的简单电子秒表设计示例，适用于Vivado 2018.3版本及Artix-7 FPGA。由于实际项目中数码管驱动、按键处理和精确时钟源（如PLL）配置较为复杂，这里仅提供核心计数逻辑部分，并假设您已有合适的按键输入模块、数码管显示驱动模块以及一个50MHz的系统时钟。

module stopwatch(
    input wire clk,      // 50MHz system clock
    input wire rst_n,    // Active low reset
    input wire start,    // Start/Resume button
    input wire stop,     // Stop/Pause button
    input wire reset,    // Reset to zero button
    output reg [63:0] time_data,   // Time data for display (ms precision)
    output reg [3:0] records[6:0]  // Array to store up to 7 records
);

// Internal counter for ms precision
reg [31:0] ms_counter;

// State machine states
typedef enum {IDLE, RUNNING, STOPPED} STATES;
reg [1:0] state;

// Record saving logic
integer record_index;
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        record_index <= 0;
        for (int i = 0; i < 7; i = i + 1)
            records[i] <= 0;
    end else begin
        if (reset && state != IDLE) begin
            record_index <= 0;
            time_data <= 0;
        end else if (start && state == IDLE || state == STOPPED) begin
            state <= RUNNING;
        end else if (stop && state == RUNNING) begin
            state <= STOPPED;
            records[record_index] <= ms_counter;
            record_index <= (record_index == 6) ? 0 : record_index + 1;
        end
    end
end

// Timer increment logic
always @(posedge clk or negedge rst_n) begin
    if (~rst_n) begin
        ms_counter <= 0;
    end else if (state == RUNNING) begin
        ms_counter <= ms_counter + 1'b1;
        // Every 1000 ms, increment seconds, minutes and hours counters
        // (omitted here, you'll need to implement this based on your display format)
    end
end

// Output the current time_data to the display driver
assign time_data = ms_counter; // Simplified for illustration, needs to be converted to HH:MM:SS:MS format

endmodule

注意：上述代码并未包含时分秒毫秒转换的具体逻辑，这部分需要根据数码管显示的实际需求来编写，通常会涉及进位和非线性编码。同时，按键处理也做了简化处理，实际应用中需要对按键去抖动等操作进行优化。

此外，上板前还需要确保你的FPGA设计已经包含了所有必要的外围模块，例如用于捕获按键信号的IO引脚、用于驱动数码管的SEGMENT DRIVER模块以及PLL模块以获得精确的时间基准。