加法计数器代码module project_11r(clk,Q) ;
input clk ;
output[3 :0] Q ;
reg[3 :0] Q ;
always @(posedge clk)
begin Q<=Q+1 ;
end endmodule
激励文件module project11sim;
reg clk;
wire [3:0] Q;
initial begin
clk = 0;
end
always #5 begin
clk = ~clk;
end
project_11r uut(
.clk(clk),.Q(Q)
);
endmodule
但是波形图出现红线
