关于Verilog编写状态机的test文件问题

Question

module test();
wire a,b,clk,C,X,reset;
reg a1,b1,reset1,clk1;
initial begin
assign reset1=0;
assign a1=0;
assign b1=0;
assign clk1=0;
end
always #10 a1=!a1;
always #5 b1=!b1;
always #5 clk1=!clk1;
initial
#10 reset1=1;
assign reset=reset1;
assign clk=clk1;
assign a=a1;
assign b=b1;
transformation T1(
.reset(reset),
.clk(clk),
.a(a),
.b(b),
.C(C),
.X(X)
);
endmodule
这是我的test代码，出来之后除了C和X的值都为0是为什么？

Answer 1

https://zhidao.baidu.com/question/369320856356768324.html