我的顶层代码
module top
(
input clk,
input rst_n,
output [13:0] sine
);
wire [31:0] phi_inc_i;
wire clken;
wire [13:0] phase_mod_i;
wire out_valid;
assign clken = 1'b1;
assign phi_inc_i = 32'd42949673;
assign phase_mod_i = 14'b10_0110_0000_1111;
nco_100M_1M inst1(
.phi_inc_i (phi_inc_i) ,
.clk (clk) ,
.reset_n (rst_n) ,
.clken (clken) ,
.phase_mod_i (phase_mod_i) ,
.fsin_o (sine) ,
.out_valid (out_valid )
);
endmodule
我的测试文件
`timescale 1ns / 1ns
module tb();
reg rst1;
reg clk;
wire [13:0] SI;
top t1(
.rst_n(rst1),
.clk(clk),
.sine(SI));
parameter PERIOD = 10; // 设置系统时钟为50Mhz
always #10 clk = ~clk;
initial begin
clk = 1'b0; #40;
rst1 = 1'b0; #40;
rst1 = 1'b1;
end
endmodule