HDLbits Multipluxers这一节
问题题干:
Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.
代码
module top_module(
input [1023:0] in,
input [7:0] sel,
output [3:0] out );
//正确答案为:
assign out = {in[sel * 4 + 3], in[sel * 4 + 2], in[sel * 4 + 1], in[sel * 4]};
//为什么 assign out=in[sel * 4 + 3:sel * 4]; 会报错
endmodule
为什么用:assign out=in[sel * 4 + 3:sel * 4]; 编译就会报错,显示sel不是一个constant value?